Abstract: Method and apparatus for controlling latch-up in a CMOS circuit senses a power supply transition, clamps the substrate to ground in response to sensing a power supply transition, and releases the clamp after the power supply transition. A charge pump pumps the substrate illustratively to -3 volts. The charge pump, clamping transistor and related elements are on the same CMOS substrate where latch-up is to be controlled. The substrate to ground capacitance of the substrate is increased to prevent localized substrate voltage disturbances which may induce latch-up.

Abstract: A dynamic random access memory cell (30) includes an access transistor (32) having the gate terminal thereof connected to a word line (34) and the source and drain terminals thereof connected between a bit line (36) and a node (37). A charge storage capacitor (38) is connected between the node (37) and a decoded plate line (40). The plate line (40) receives a bi-level voltage which shifts levels in a timing sequence keyed to the word line (34) signal. Shifting of voltage levels provided to the capacitor (38) through the plate line (40) essentially doubles the signal margin of the memory circuit (30) to thereby enhance the reliability of the data stored in the memory circuit (30).

Abstract: A trigger circuit is described for use in an MOS clock generator. The clock generator is the type which uses a conventional double bootstrapping circuit coupled to a control transistor to develop a high level clock output signal. The trigger circuit preconditions the control transistor to facilitate proper bootstrapping operation. Included in the trigger circuit is a plurality of interconnected transistors which respond to a pre-charge signal and then a warmup signal for turning the control transistor off and then for establishing selected potentials at the electrodes of the control transistor to precondition it for bootstrapping. In response to a subsequent trigger signal, the trigger circuit enables the control transistor for developing a high level clock output signal.

Abstract: A redundancy scheme is described for replacing defective main memory cells in a dynamic RAM with spare memory cells. The spare cells are arranged in groups of spare rows and spare columns of memory cells such that a plurality of groups of spare rows and columns of cells are substituted for defective main rows and columns of cells so as to repair relatively large defects which impair adjacent rows and columns of main memory cells. In the preferred embodiment, the RAM includes a plurality of address buffers, each of which receives an incoming row address bit and then an incoming column address bit for sequentially outputting row and column address data. Associated with each buffer is a store for a defective row address, a store for a defective column address, and a comparator. The stores retain defective memory cell addresses which the comparator sequentially compares against the address data sequentially output by the buffer.

Abstract: A dummy cell arrangement is described for sensing the logic state of an accessed memory cell in an MOS memory in which a memory cell capacitor of a given size is associated with each memory cell. In the preferred embodiment, a plurality of dummy cells are included, each of which has a dummy capacitor of substantially the same given size as a memory cell capacitor. When the state of an accessed memory cell is to be sensed, its memory cell capacitor is coupled to a bit line to change the voltage thereon and a selected dummy cell capacitor is coupled to a pair of bit lines so as to effect substantially equal transfers of charge between the dummy capacitor and the bit lines to which it is coupled. The resulting voltage on the memory cell capacitor's bit line is compared to the voltage on one of the dummy capacitor's bit lines so as to determine the logic state of the accessed memory cell.

Abstract: A high voltage clock generator including an isolation and precharge circuit to charge a bootstrap capacitance at a time prior to driving the load capacitance to a higher voltage level. The first clock generator charges a load capacitance to the initial voltage level while the isolation precharge circuit has already acted to charge the bootstrap capacitance. A second clock generator drives the bootstrap capacitance to a higher voltage level, at which time the isolation precharge circuit acts to engage the bootstrap capacitance to the load capacitance and charge the load capacitance to a higher voltage level.

Abstract: A folded bit line-shared sense amplifier arrangement is described for sensing the logic state of an accessed memory cell in a dynamic MOS random access memory. In the preferred embodiment, a shared sense amplifier is positioned between and coupled to first and second bit lines via first and second isolation transistors. The same shared sense amplifier is also positioned between and coupled to third and fourth bit lines via third and fourth isolation transistors. When the state of an accessed memory cell is to be sensed, its memory cell capacitor is coupled to a selected bit line and a dummy cell capacitor is coupled to the bit line adjacent the selected bit line. A decoding circuit selectively activates the shared sense amplifier to sense a difference in voltage between the selected bit line and its adjacent bit line so as to determine the logic state associated with the accessed memory cell. Then, the sense amplifier latches into this logic state for reading by the input/output buss lines.

Abstract: A system is described for use in a semiconductor memory for rapidly transferring data between a plurality of successive memory locations and a data output buss. The system includes a plurality of data latches for storing data derived from successive locations in memory, and a corresponding plurality of serially coupled decoders, each associated with one of the data latches. In response to an address input, one decoder is enabled for causing its associated data latch to output its stored data to the data buss. The latter decoder then disables itself and enables the next decoder so that a second latch outputs its stored data. The process continues with each decoder disabling itself and enabling the next decoder so that the data latches are caused to sequentially output their stored data.

Abstract: A refresh counter which uses existing address buffers and is implemented with refresh address storage and decoders. The address buffers act to multiplex the refresh address storage outputs as inverted outputs when properly enabled. When all lower order bits are true at a particular unit of the refresh counter and a transfer clock signal occurs, the outputs of the buffer are transferred to the refresh storage where the buffer multiplexes them when enabled. The clocking scheme is structured to enable only at the end of a refresh cycle. In this manner, the counter is incremented at the end of each refresh cycle.

Abstract: An AND-gate clock having an input stage, an output stage, and an isolation stage. The input stage receives two signals, and gates them to produce a high signal. The output stage is used to drive a load typically having a large load capacitance when both signals are true. The isolation stage isolates the input stage from the output stage when only one signal is true, therefore preventing power dissipation by current flow through the output driver stage. The isolation stage provides an alternative current path through smaller transistors, thereby incurring lesser power dissipation and requiring less layout area. A small driver stage may then be used.

Abstract: Voltage boosting circuits of a type using a plurality of inverters with parallelled inputs, each inverter arranged to pump charge into a respective pair of booster capacitors--rather than one respective booster capacitor--to develop an output voltage in each stage which is doubled in amplitude over the voltage used to power the inverter in that stage. To this end, the inverter in each successive stage of the voltage boosting circuit is powered by the output voltage of the preceding stage.