Abstract: Systems and methods are provided for packet detection in a wireless local area network transceiver. An antenna is configured to receive a signal, having a carrier frequency. A mixer is configured to mix the received signal with one of the in-phase and quadrature components of the local oscillator to produce a corresponding one of an in-phase downconverted signal and a quadrature phase downconverted signal. A packet detector is configured to determine, from the one of the in-phase downconverted signal and the quadrature phase downconverted signal, if the signal contains a packet of data and instruct a set of components associated with an other of the in-phase and quadrature components of the local oscillator to activate to process the received signal.

Abstract: Systems and methods are provided for packet detection in a wireless local area network transceiver. An antenna is configured to receive a signal, having a carrier frequency. A mixer is configured to mix the received signal with one of the in-phase and quadrature components of the local oscillator to produce a corresponding one of an in-phase downconverted signal and a quadrature phase downconverted signal. A packet detector is configured to determine, from the one of the in-phase downconverted signal and the quadrature phase downconverted signal, if the signal contains a packet of data and instruct a set of components associated with an other of the in-phase and quadrature components of the local oscillator to activate to process the received signal.

Abstract: A receiver is configured to use a first part of a received signal and a second part of the received signal to determine, respectively, a first estimate and a second estimate of the channel. The first and second parts carry information for decoding the received signal in a first protocol and in a second protocol, respectively. A final estimate of the channel is performed from the first and the second estimates. The final estimate is then used for decoding the data in the received signal according to one of the protocols. A carrier frequency offset from a set of symbols occurring prior to preamble symbols is determined and is corrected for decoding the preamble symbols. The corrected preamble symbols are then used for estimating the channel. In one embodiment, the carrier frequency offset is determined for the multiple antenna packet format used in the 802.11n standard.

Abstract: A receiver is configured to use a first part of a received signal and a second part of the received signal to determine, respectively, a first estimate and a second estimate of the channel. The first and second parts carry information for decoding the received signal in a first protocol and in a second protocol, respectively. A final estimate of the channel is performed from the first and the second estimates. The final estimate is then used for decoding the data in the received signal according to one of the protocols. A carrier frequency offset from a set of symbols occurring prior to preamble symbols is determined and is corrected for decoding the preamble symbols. The corrected preamble symbols are then used for estimating the channel. In one embodiment, the carrier frequency offset is determined for the multiple antenna packet format used in the 802.11n standard.

Abstract: A peak-to-average ratio (PAR) of a signal is reduced by clipping the signal at a threshold level and replacing desired frequency tones of the clipped signal with set of frequency tones of the signal. In one embodiment, the PAR of a signal is reduced by adding a peak cancellation signal to the received signal. The peak cancellation signal is generated by clipping the received signal at a threshold level and generating a difference signal by subtracting the received signal from the clipped signal. The peak cancellation signal thus generated is scaled by a scaling factor and added to the received signal to reduce the PAR of the received signal. The scaling factor is adjusted to maintain the desired quality of the received signal. In one embodiment, the PAR of an orthogonal frequency division multiplexed (OFDM) signal may be reduced.

Abstract: A peak-to-average ratio (PAR) of a signal is reduced by clipping the signal at a threshold level and replacing desired frequency tones of the clipped signal with set of frequency tones of the signal. In one embodiment, the PAR of a signal is reduced by adding a peak cancellation signal to the received signal. The peak cancellation signal is generated by clipping the received signal at a threshold level and generating a difference signal by subtracting the received signal from the clipped signal. The peak cancellation signal thus generated is scaled by a scaling factor and added to the received signal to reduce the PAR of the received signal. The scaling factor is adjusted to maintain the desired quality of the received signal. In one embodiment, the PAR of an orthogonal frequency division multiplexed (OFDM) signal may be reduced.

Abstract: An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss.

Abstract: A receiver in a packet based communication system includes a programmable block and a detection block that detects at least one of an operating condition of the receiver and a protocol condition of the communication system. Further, the receiver includes a control circuit coupled to the programmable block that controls the programmable block to transition to a set of radio modes according to at least one of the operating condition and the protocol condition.

Abstract: An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss.

Abstract: A method of achieving reduced modulation range requirement in a Digitally Controlled Oscillator (DCO) which is deployed as part of a DRP (Digital Radio Processor) and tuned to a tuning frequency range having operating-channel center-frequencies, wherein phase difference between consecutive samples is termed as FCW (Frequency Control Word), uses the steps of digitally modifying and limiting the FCW so that the FCW does not exceed known FCW thresholds, e.g., chosen from ?/2, ?/4, ?/8, and redistributing the FCWs while maintaining a cumulative sum of phases and without significant EVM (Error Vector Magnitude) degradation. The FCW threshold can be chosen arbitrarily and need not be in the form of ?/2n. The method uses a FCW limiting algorithm which reduces supply voltage sensitivity of the DCO and enables significant reduction in area of capacitor bank which would be otherwise needed.

Abstract: An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss.

Abstract: An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss.

Abstract: A receiver in a packet based communication system includes a programmable block and a detection block that detects at least one of an operating condition of the receiver and a protocol condition of the communication system. Further, the receiver includes a control circuit coupled to the programmable block that controls the programmable block to transition to a set of radio modes according to at least one of the operating condition and the protocol condition.

Abstract: A multi-carrier (MC) receiver receives a multi-carrier signal containing data symbols as well as pilot symbols. The MC receiver estimates a carrier frequency offset in a downconverted base-band multi-carrier signal in the frequency domain based on deviations of one or more characteristics of the pilot signals from predetermined values, and corrects for the offset in the time domain. In an embodiment, a second order phase locked loop (PLL) estimates the phase of the pilot signals to determine the carrier frequency offset. Changes in pilot phases caused due to the time domain correction are cancelled to allow the PLL to minimize deviations from the lock position.

Abstract: A method of achieving reduced modulation range requirement in a Digitally Controlled Oscillator (DCO) which is deployed as part of a DRP (Digital Radio Processor) and tuned to a tuning frequency range having operating-channel center-frequencies, wherein phase difference between consecutive samples is termed as FCW (Frequency Control Word), uses the steps of digitally modifying and limiting the FCW so that the FCW does not exceed known FCW thresholds, e.g., chosen from ?/2, ?/4, ?/8, and redistributing the FCWs while maintaining a cumulative sum of phases and without significant EVM (Error Vector Magnitude) degradation. The FCW threshold can be chosen arbitrarily and need not be in the form of ?/2n. The method uses a FCW limiting algorithm which reduces supply voltage sensitivity of the DCO and enables significant reduction in area of capacitor bank which would be otherwise needed.

Abstract: A method for fabricating a flash memory device having a self-aligned source includes providing a semiconductor substrate having a source region separated from a drain region by a channel region. The method also includes forming an isolation structure in the semiconductor substrate that crosses the source, drain, and channel regions of the semiconductor substrate. The method also includes forming a continuous stack structure outwardly from the channel region of the semiconductor substrate and the isolation structure. The method includes depositing a bottom anti-reflective layer over the semiconductor substrate, the isolation structure and the stack structure to substantially uniformly planarize the semiconductor substrate and the isolation structure. The method further includes depositing a photoresist layer over select portions of the bottom anti-reflective layer and the continuous stack structure to form a self-aligned source pattern using a photo mask.

Abstract: A method of fabricating a semiconductor device having a memory array (9) that includes a source line (24) is provided. The method of forming the source line (24) may include providing a semiconductor substrate (52) having a source region (60) separated from a drain region (62) by a channel region (64). An isolation structure (70) may be formed in the semiconductor substrate (52). The isolation structure (70) may cross the source region (60), the drain region (62), and the channel region (64) of the semiconductor substrate (52). An isolation dielectric material (78) may be formed within the isolation structure (70). A continuous stack structure (50) may be formed outwardly from the channel region (64) of the semiconductor substrate (52) and the isolation structure (70). A first photomask (100) may be formed outwardly from the continuous stack structure (50) and the semiconductor substrate (52).

Abstract: An improved apparatus and process for detecting aberrations in production process operations is provided. In one embodiment, operations of a plasma etch reactor (10) are monitored to detect aberrations in etching operations. A reference end-point trace (EPT) is defined (62) for the etch process. Regions are defined in the reference end-point trace (70) and characteristics and tolerances for each region are defined (72-80). The etcher is run and an actual EPT is obtained (82) from the running of the etcher. The actual EPT is analyzed to identify proposed regions of the actual EPT (86), and then the proposed regions of the actual EPT are matched with regions of the reference EPT (96). The system employs a series of heuristic functions in matching proposed regions of the actual EPT with regions of the reference EPT.