Patents by Inventor Sasangan Ramanathan

Sasangan Ramanathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9159608
    Abstract: There is disclosed a method for forming a TiSiN thin film on a substrate according to ALD including a first process of preheating a substrate while supplying Ar or N2 containing inert gas to a chamber, after disposing a substrate in a chamber; a second process of forming a TiN film on the substrate by repeating at least one time a process of purging over-supplied Ti containing gas after supplying Ti containing gas and inert gas after that and a process of purging residual product after supplying N containing gas and inert gas after that; a third process of forming a SiN film by repeating at least one time a process of purging over-supplied Si containing gas after supplying Si containing gas on the TiN film and supplying inert gas after that and a process of purging residual product after supplying N containing gas and supplying inert gas after that; and a fourth process of forming a TiSiN film having a desired thickness by repeating the second and third processes at least one time, a partial pressure range of
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: October 13, 2015
    Assignee: Aixtron SE
    Inventors: Woong Park, Young Jin Jang, Gi Youl Kim, Brian Lu, Greg Siu, Hugo Silva, Sasangan Ramanathan
  • Publication number: 20150050806
    Abstract: There is disclosed a method for forming a TiSiN thin film on a substrate according to ALD including a first process of preheating a substrate while supplying Ar or N2 containing inert gas to a chamber, after disposing a substrate in a chamber; a second process of forming a TiN film on the substrate by repeating at least one time a process of purging over-supplied Ti containing gas after supplying Ti containing gas and inert gas after that and a process of purging residual product after supplying N containing gas and inert gas after that; a third process of forming a SiN film by repeating at least one time a process of purging over-supplied Si containing gas after supplying Si containing gas on the TiN film and supplying inert gas after that and a process of purging residual product after supplying N containing gas and supplying inert gas after that; and a fourth process of forming a TiSiN film having a desired thickness by repeating the second and third processes at least one time, a partial pressure range of
    Type: Application
    Filed: April 8, 2013
    Publication date: February 19, 2015
    Inventors: Woong Park, Young Jin Jang, Gi Youl Kim, Brian Lu, Greg Siu, Hugo Silva, Sasangan Ramanathan
  • Patent number: 7981473
    Abstract: A process in which a wafer is exposed to a first chemically reactive precursor dose insufficient to result in a maximum saturated ALD deposition rate on the wafer, and then to a second chemically reactive precursor dose, the precursors being distributed in a manner so as to provide substantially uniform film deposition. The second chemically reactive precursor dose may likewise be insufficient to result in a maximum saturated ALD deposition rate on the wafer or, alternatively, sufficient to result in a starved saturating deposition on the wafer. The process may or may not include purges between the precursor exposures, or between one set of exposures and not another.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: July 19, 2011
    Assignee: Aixtron, Inc.
    Inventors: Gi Youl Kim, Anuranjan Srivastava, Thomas E. Seidel, Ana R. Londergan, Sasangan Ramanathan
  • Publication number: 20080131601
    Abstract: A process in which a wafer is exposed to a first chemically reactive precursor dose insufficient to result in a maximum saturated ALD deposition rate on the wafer, and then to a second chemically reactive precursor dose, the precursors being distributed in a manner so as to provide substantially uniform film deposition. The second chemically reactive precursor dose may likewise be insufficient to result in a maximum saturated ALD deposition rate on the wafer or, alternatively, sufficient to result in a starved saturating deposition on the wafer. The process may or may not include purges between the precursor exposures, or between one set of exposures and not another.
    Type: Application
    Filed: March 1, 2004
    Publication date: June 5, 2008
    Inventors: Gi Youl Kim, Anuranjan Srivastava, Thomas E. Seidel, Ana R. Londergan, Sasangan Ramanathan
  • Publication number: 20060137609
    Abstract: A wafer processing apparatus includes one or more processing modules, each having multiple, distinct, single-wafer processing reactors configured for semi-independent ALD and/or CVD film deposition therein; a robotic central wafer handler configured to provide wafers to and accept wafers from each of said wafer processing modules; and a single-wafer loading and unloading mechanism that includes a loading and unloading port and a mini-environment coupling the loading and unloading port to the robotic central wafer handler. The wafer processing reactors may be arranged (i) along axes of a Cartesian coordinate system, or (ii) in quadrants defined by said axes, one axis being parallel to a wafer input plane of the at least one of the process modules to which the single-wafer processing reactors belong. Each processing module can include up to four single-wafer processing reactors, each with an independent gas distribution module.
    Type: Application
    Filed: September 12, 2005
    Publication date: June 29, 2006
    Inventors: Jerzy Puchacz, Sasangan Ramanathan, Manolito Reyes, Thomas Seidel
  • Patent number: 6951765
    Abstract: The present invention pertains to apparatus and methods for introduction of solid precursors and reactants into a supercritical fluid reactor. Solids are dissolved in supercritical fluid solvents in generator apparatus separate from the supercritical fluid reactor. Such apparatus preferably generate saturated solutions of solid precursors via recirculation of supercritical fluids through a vessel containing the solid precursors. Supercritical solutions of the solids are introduced into the reactor, which itself is charged with a supercritical fluid. Supercritical conditions are maintained during the delivery of the dissolved precursor to the reactor. Recirculation of supercritical precursor solutions through the reactor may or may not be implemented in methods of the invention. Methods of the invention are particularly well suited for integrated circuit fabrication, where films are deposited on wafers under supercritical conditions.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: October 4, 2005
    Assignee: Novellus Systems, Inc.
    Inventors: Sanjay Gopinath, Patrick A. Van Cleemput, Michelle Schulberg, Sasangan Ramanathan, Francisco Juarez, Patrick Joyce
  • Patent number: 6887781
    Abstract: Electronic components such as semiconductor wafer VLSI and ULSI integrated circuit devices are provided having a robust barrier layer in the device interconnects. The robust barrier layer provides excellent step coverage, low resistance and enhanced adhesion to CVD copper and the interconnect has a double structure of a layer of a barrier material and a metal layer thereon. The metal layer is preferably tungsten and is formed by replacing silicon or other such atoms on the surface of the barrier layer with tungsten metal. A layer of silicon can be formed on the barrier layer, silicon atoms can be formed on the surface by reacting the barrier layer with a silicon containing reactant or a silicon containing barrier layer can be used.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: May 3, 2005
    Assignee: Novellus Systems, Inc.
    Inventors: Sang-Hyeob Lee, Sasangan Ramanathan
  • Publication number: 20050016956
    Abstract: Different periods of an ALD cycle are performed using different purge flows and, in some cases, different pumping capacities, while maintaining the reactor chamber at a nominally constant pressure. The purge flows may, in some cases, utilize different gasses and/or may be provided through different flow paths. These operations provide for ALD cycle time improvements and economical operation with respect to consumables usage. In some embodiments the use of an annular throttle valve provides a means for controlling downstream flow limiting conductances in a gas flow path from the reactor chamber.
    Type: Application
    Filed: March 1, 2004
    Publication date: January 27, 2005
    Inventors: Xinye Liu, Thomas Seidel, Edward Lee, Ken Doering, Sasangan Ramanathan
  • Patent number: 6720259
    Abstract: A method to deposit a passivating layer of a first material on an interior reactor surface of a cold or warm wall reactor, in which the first material is non-reactive with one or more precursor used to form a second materials. Subsequently when a film layer is deposited on a substrate by subjecting the substrate to the one or more precursors, in which at least one precursor has a low vapor pressure, uniformity and repeatability is improved by the passivation layer.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: April 13, 2004
    Assignee: Genus, Inc.
    Inventors: Ana R. Londergan, Sasangan Ramanathan, Jereld Winkler, Thomas E. Seidel
  • Publication number: 20040023516
    Abstract: A method to deposit a passivating layer of a first material on an interior reactor surface of a cold or warm wall reactor, in which the first material is non-reactive with one or more precursors used to form a second material. Subsequently when a film layer is deposited on a substrate by subjecting the substrate to the one or more precursors, in which at least one precursor has a low vapor pressure, uniformity and repeatability is improved by the passivation layer.
    Type: Application
    Filed: October 2, 2002
    Publication date: February 5, 2004
    Inventors: Ana R. Londergan, Sasangan Ramanathan, Jereld Winkler, Thomas E. Seidel
  • Publication number: 20030194858
    Abstract: Electronic components such as semiconductor wafer VLSI and ULSI integrated circuit devices are provided having a robust barrier layer in the device interconnects. The robust barrier layer provides excellent step coverage, low resistance and enhanced adhesion to CVD copper and the interconnect has a double structure of a layer of a barrier material and a metal layer thereon. The metal layer is preferably tungsten and is formed by replacing silicon or other such atoms on the surface of the barrier layer with tungsten metal. A layer of silicon can be formed on the barrier layer, silicon atoms can be formed on the surface by reacting the barrier layer with a silicon containing reactant or a silicon containing barrier layer can be used.
    Type: Application
    Filed: April 29, 2003
    Publication date: October 16, 2003
    Applicant: Novellus Systems, Inc.
    Inventors: Sang-Hyoeb Lee, Sasangan Ramanathan
  • Patent number: 6589887
    Abstract: The present invention pertains to methods for forming metal-derived layers on substrates. Preferred methods apply to integrated circuit fabrication. In particular, selective methods may be used to form diffusion barriers on partially fabricated integrated circuits. In one preferred method, a wafer is heated and exposed to a metal vapor. Under specific conditions, the metal vapor reacts with dielectric surfaces to form a diffusion barrier, but does not react with metal surfaces. Thus, methods of the invention form diffusion barriers that selectively protect dielectric surfaces but leave metal surfaces free of diffusion barrier.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: July 8, 2003
    Assignee: Novellus Systems, Inc.
    Inventors: Jeremie Dalton, Ronald A. Powell, Sridhar K. Kailasam, Sasangan Ramanathan
  • Publication number: 20020081845
    Abstract: Electronic components such as semiconductor wafer VLSI and ULSI integrated circuit devices are provided having a robust barrier layer in the device interconnects. The robust barrier layer provides excellent step coverage, low resistance and enhanced adhesion to CVD copper and the interconnect has a double structure of a layer of a barrier material and a metal layer thereon. The metal layer is preferably tungsten and is formed by replacing silicon or other such atoms on the surface of the barrier layer with tungsten metal. A layer of silicon can be formed on the barrier layer, silicon atoms can be formed on the surface by reacting the barrier layer with a silicon containing reactant or a silicon containing barrier layer can be used.
    Type: Application
    Filed: December 27, 2000
    Publication date: June 27, 2002
    Applicant: Novellus Systems, Inc.
    Inventors: Sang-Hyeob Lee, Sasangan Ramanathan
  • Patent number: 6071555
    Abstract: Thin films of ferroelectric composite material comprising barium strontium titanate (BSTO) combined with magnesium oxide additive are produced by metalorganic decomposition. The barium strontium titanate magnesium oxide ferroelectric composite comprises Ba.sub.1-x Sr.sub.x TiO.sub.3 /MgO, wherein x is greater than 0.0 but less than or equal to 0.75 and preferably is 0.4, and wherein the weight ratio of BSTO to magnesium oxide may range from 99 to 40 weight percent BSTO to 1 to 60 weight percent magnesium oxide. These films have desirable electronic properties and may have application to both active microwave and dynamic random access memory devices, including low dielectric constant, low loss factor, high tunability, and high resistivity. The films produced are uniformly thick and impurity free, with thicknesses of only 0.4 microns.
    Type: Grant
    Filed: November 5, 1998
    Date of Patent: June 6, 2000
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Somnath Sengupta, Steven Stowell, Louise Sengupta, Pooran C. Joshi, Sasangan Ramanathan, Seshu B. Desu
  • Patent number: 6015759
    Abstract: Deposition rates of undoped silicate glass dielectric layers on thermal oxide are increased by pre-treating the thermal oxide layer with electromagnetic radiation in the ultraviolet (UV) and/or vacuum ultraviolet (VUV) wavelengths. The surface smoothness of the resulting films are also increased by pre-treating films with UV and/or VUV radiation. Furthermore, the gap filling abilities of the undoped silicate glass films are increased by pre-treating the thermal oxide with UV and/or VUV radiation. New equipment and methods are presented for exposing semiconductor devices to UV and/or VUV radiation, and for enhancing the deposition rates and film quality for semiconductor manufacture. Semiconductor devices incorporating the new methods are also described.
    Type: Grant
    Filed: December 8, 1997
    Date of Patent: January 18, 2000
    Assignee: Quester Technology, Inc.
    Inventors: Ashraf R. Khan, Sasangan Ramanathan, Giovanni Antonio Foggiato
  • Patent number: 5887117
    Abstract: A device and method for flash evaporating a reagent includes an evaporation chamber that houses a dome on which evaporation occurs. The dome is solid and of high thermal conductivity and mass, and may be heated to a temperature sufficient to vaporize a specific reagent. The reagent is supplied from an external source to the dome through a nozzle, and may be supplied as a continuous stream, as a shower, and as discrete drops. A carrier gas may be introduced into the evaporation chamber and create a vortex flow therewithin. After evaporation, the gas vapor may be removed from the evaporation chamber through a regulating valve to a reaction chamber. Another embodiment of the invention includes a plurality of evaporating domes that separately receive reagent, and may receive reagents of differing composition.
    Type: Grant
    Filed: January 2, 1997
    Date of Patent: March 23, 1999
    Assignees: Sharp Kabushiki Kaisha, Virginia Tech Intellectual Properties, Inc.
    Inventors: Seshu Babu Desu, Sasangan Ramanathan, Carlos Tres Avala Suchicital