Patents by Inventor Satoru Sueki
Satoru Sueki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8513034Abstract: A method of manufacturing a layered chip package that includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of layer portions. The method includes fabricating a plurality of substructures, and completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the wiring on the main body.Type: GrantFiled: April 22, 2011Date of Patent: August 20, 2013Assignees: Headway Technologies, Inc., TDK Corporation, SAE Magnetics (H.K.) Ltd.Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
-
Patent number: 8324741Abstract: A layered chip package has a main body including pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The pairs of layer portions include specific pairs of layer portions. Each of the specific pairs of layer portions includes a first-type layer portion and a second-type layer portion. The first-type layer portion includes electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes. The specific pairs of layer portions are provided in an even number.Type: GrantFiled: May 16, 2011Date of Patent: December 4, 2012Assignees: Headway Technologies, Inc., TDK Corporation, SAE Magnetics (H.K.) Ltd.Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
-
Patent number: 8154116Abstract: A layered chip package includes: a plurality of layer portions stacked, each of the layer portions including a semiconductor chip; and a heat sink. Each of the plurality of layer portions has a top surface, a bottom surface, and four side surfaces. The heat sink has at least one first portion, and a second portion coupled to the at least one first portion. The at least one first portion is adjacent to the top surface or the bottom surface of at least one of the layer portions. The second portion is adjacent to one of the side surfaces of each of at least two of the plurality of layer portions.Type: GrantFiled: November 3, 2008Date of Patent: April 10, 2012Assignees: HeadwayTechnologies, Inc., TDK Corporation, SAE Magnetics (H.K.) Ltd.Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
-
Patent number: 8134229Abstract: A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed.Type: GrantFiled: September 2, 2010Date of Patent: March 13, 2012Assignees: Headway Technologies, Inc., TDK CorporationInventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki
-
Publication number: 20110221073Abstract: A layered chip package has a main body including pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The pairs of layer portions include specific pairs of layer portions. Each of the specific pairs of layer portions includes a first-type layer portion and a second-type layer portion. The first-type layer portion includes electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes. The specific pairs of layer portions are provided in an even number.Type: ApplicationFiled: May 16, 2011Publication date: September 15, 2011Applicants: HEADWAY TECHNOLOGIES, INC., SAE MAGNETICS (H.K.) LTD., TDK CORPORATIONInventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
-
Publication number: 20110201137Abstract: A method of manufacturing a layered chip package that includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of layer portions. The method includes fabricating a plurality of substructures, and completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the wiring on the main body.Type: ApplicationFiled: April 22, 2011Publication date: August 18, 2011Applicants: HEADWAY TECHNOLOGIES, INC., TDK CORPORATION, SAE MAGNETICS (H.K.) LTD.Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
-
Patent number: 7968374Abstract: A layered chip package has a main body including pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The pairs of layer portions include at least one specific pair of layer portions including a first-type layer portion and a second-type layer portion. The first-type layer portion includes electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes.Type: GrantFiled: February 6, 2009Date of Patent: June 28, 2011Assignees: Headway Technologies, Inc., TDK Corporation, SAE Magnetics (H.K.) Ltd.Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
-
Patent number: 7964976Abstract: A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. The plurality of layer portions include at least one layer portion of a first type and at least one layer portion of a second type. The layer portions of the first and second types each include a semiconductor chip. The layer portion of the first type further includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the layer portion of the second type does not include any electrode connected to the semiconductor chip and having an end face located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end face of each of the plurality of electrodes.Type: GrantFiled: August 20, 2008Date of Patent: June 21, 2011Assignees: Headway Technologies, Inc., TDK Corporation, SAE Magnetics (H.K.) Ltd.Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
-
Patent number: 7868442Abstract: A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure.Type: GrantFiled: June 30, 2008Date of Patent: January 11, 2011Assignees: Headway Technologies, Inc., TDK CorporationInventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki
-
Patent number: 7863095Abstract: A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure.Type: GrantFiled: July 30, 2010Date of Patent: January 4, 2011Assignees: Headway Technologies, Inc., TDK CorporationInventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki
-
Publication number: 20100327464Abstract: A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed.Type: ApplicationFiled: September 2, 2010Publication date: December 30, 2010Applicants: HEADWAY TECHNOLOGIES, INC., TDK CORPORATIONInventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki
-
Patent number: 7846772Abstract: A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. To manufacture the layered chip package, a layered chip package substructure is fabricated by: processing a semiconductor wafer to form a plurality of pre-semiconductor-chip portions aligned; forming at least one groove extending to be adjacent to at least one of the pre-semiconductor-chip portions; forming an insulating layer to fill the groove; and forming the electrodes.Type: GrantFiled: June 23, 2008Date of Patent: December 7, 2010Assignees: Headway Technologies, Inc., TDK CorporationInventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki
-
Publication number: 20100304531Abstract: A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure.Type: ApplicationFiled: July 30, 2010Publication date: December 2, 2010Applicants: HEADWAY TECHNOLOGIES, INC., TDK CORPORATIONInventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki
-
Publication number: 20100200977Abstract: A layered chip package has a main body including a plurality of pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The plurality of pairs of layer portions include at least one specific pair of layer portions consisting of a first-type layer portion and a second-type layer portion. The first-type layer portion includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes.Type: ApplicationFiled: February 6, 2009Publication date: August 12, 2010Applicants: HEADWAY TECHNOLOGIES, INC., TDK CORPORATION, SAE MAGNETICS (H.K.) LTD.Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
-
Patent number: 7767494Abstract: A manufacturing method for a layered chip package including a stack of a plurality of layer portions includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure.Type: GrantFiled: June 30, 2008Date of Patent: August 3, 2010Assignees: Headway Technologies, Inc., TDK CorporationInventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki
-
Patent number: 7745259Abstract: A layered chip package includes: a main body including a plurality of layer portions; wiring disposed on a side surface of the main body; a plurality of first terminals disposed on a top surface of the main body; and a plurality of second terminals disposed on a bottom surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions, and to the plurality of first and second terminals.Type: GrantFiled: June 30, 2008Date of Patent: June 29, 2010Assignees: Headway Technologies, Inc., TDK CorporationInventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki
-
Publication number: 20100109137Abstract: A layered chip package includes: a plurality of layer portions stacked, each of the layer portions including a semiconductor chip; and a heat sink. Each of the plurality of layer portions has a top surface, a bottom surface, and four side surfaces. The heat sink has at least one first portion, and a second portion coupled to the at least one first portion. The at least one first portion is adjacent to the top surface or the bottom surface of at least one of the layer portions. The second portion is adjacent to one of the side surfaces of each of at least two of the plurality of layer portions.Type: ApplicationFiled: November 3, 2008Publication date: May 6, 2010Applicants: HEADWAY TECHNOLOGIES, INC., TDK CORPORATION, SAE MAGNETICS (H.K.) LTD.Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
-
Publication number: 20100044879Abstract: A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. The plurality of layer portions include at least one layer portion of a first type and at least one layer portion of a second type. The layer portions of the first and second types each include a semiconductor chip. The layer portion of the first type further includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the layer portion of the second type does not include any electrode connected to the semiconductor chip and having an end face located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end face of each of the plurality of electrodes.Type: ApplicationFiled: August 20, 2008Publication date: February 25, 2010Applicants: HEADWAY TECHNOLOGIES, INC., TDK CORPORATION, SAE MAGNETICS (H.K.) LTD.Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
-
Publication number: 20090325345Abstract: A manufacturing method for a layered chip package including a stack of a plurality of layer portions includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure.Type: ApplicationFiled: June 30, 2008Publication date: December 31, 2009Applicants: HEADWAY TECHNOLOGIES, INC., TDK CORPORATIONInventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki
-
Publication number: 20090321956Abstract: A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure.Type: ApplicationFiled: June 30, 2008Publication date: December 31, 2009Applicants: TDK CORPORATION, HEADWAY TECHONOLOGIES, INC.Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki