Patents by Inventor Satoru Takenouchi

Satoru Takenouchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6469259
    Abstract: A wiring board of the present invention readily controls a power source voltage and unwanted irradiation noises developed across a power source layer and a ground layer over a broad range of frequencies with a simple arrangement. The wiring board has an on-board surface on the surface of a dielectric substrate, on which a semiconductor device or the like is mounted, and a power source layer and a ground layer, which are made of a conductor material principally composed of at least one kind of element selected from Cu, W, and Mo, are provided on the back surface of the dielectric substrate or within the same. The periphery of at least one of low resistance areas of the power source layer and ground layer, respectively is provided with a corresponding high resistance area having a higher sheet resistance than that of the respective low resistance areas.
    Type: Grant
    Filed: February 27, 2001
    Date of Patent: October 22, 2002
    Assignee: Kyocera Corporation
    Inventors: Yoshihiro Takeshita, Shinya Terao, Satoru Takenouchi, Masaki Kaji, Ryuji Koga
  • Publication number: 20010050182
    Abstract: A wiring board of the present invention readily controls a power source voltage and unwanted irradiation noises developed across a power source layer and a ground layer over a broad range of frequencies with a simple arrangement. The wiring board has an on-board surface on the surface of a dielectric substrate, on which a semiconductor device or the like is mounted, and a power source layer and a ground layer, which are made of a conductor material principally composed of at least one kind of element selected from Cu, W, and Mo, are provided on the back surface of the dielectric substrate or within the same. The periphery of at least one of low resistance areas of the power source layer and ground layer, respectively is provided with a corresponding high resistance area having a higher sheet resistance than that of the respective low resistance areas.
    Type: Application
    Filed: February 27, 2001
    Publication date: December 13, 2001
    Inventors: Yoshihiro Takeshita, Shinya Terao, Satoru Takenouchi, Masaki Kaji, Ryuji Koga