Patents by Inventor Satoru Yuhaku
Satoru Yuhaku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7875974Abstract: To provide a stacked mounting structure in which the number of semiconductor chips that can be stacked is greater than conventionally, as well as a method for fabricating the same, each semiconductor chip has electrodes provided at least at one end in the stacked mounting structure, and a board holding the semiconductor chips at the one end is folded with at least two of the semiconductor chips being stacked so as to at least partially overlap with each other.Type: GrantFiled: December 17, 2008Date of Patent: January 25, 2011Assignee: Panasonic CorporationInventors: Manabu Gokan, Akihisa Nakahashi, Naoki Suzuki, Haneo Iwamoto, Satoru Yuhaku
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Publication number: 20090166839Abstract: A semiconductor stack device having semiconductor chips stacked therein, wherein pads 4d of an uppermost semiconductor chip 2d are disposed on the side of a base substrate 1, and the pads 4d of the semiconductor chip 2d and electrodes 8d of the base substrate 1 are connected to each other via a flexible substrate 5 having circuit components 7 mounted thereon.Type: ApplicationFiled: December 23, 2008Publication date: July 2, 2009Applicant: Panasonic CorporationInventors: Naoki Suzuki, Akihisa Nakahashi, Haneo Iwamoto, Manabu Gokan, Satoru Yuhaku
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Publication number: 20090166838Abstract: To provide a stacked mounting structure in which the number of semiconductor chips that can be stacked is greater than conventionally, as well as a method for fabricating the same, each semiconductor chip has electrodes provided at least at one end in the stacked mounting structure, and a board holding the semiconductor chips at the one end is folded with at least two of the semiconductor chips being stacked so as to at least partially overlap with each other.Type: ApplicationFiled: December 17, 2008Publication date: July 2, 2009Inventors: Manabu Gokan, Akihisa Nakahashi, Naoki Suzuki, Haneo Iwamoto, Satoru Yuhaku
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Patent number: 7488895Abstract: A component built-in module of the present invention includes: a first wiring pattern; an electronic component mounted on the first wiring pattern; a second wiring pattern; an electrical insulating sheet with the electrical component built therein, the electrical insulating sheet being disposed between the first wiring pattern and the second wiring pattern; and a via conductor formed in a via hole penetrating through the electrical insulating sheet, the via conductor connecting electrically the first wiring pattern and the second wiring pattern. A side face of the via conductor defines a continuous line in an axis direction of the via conductor. Thus, a component built-in module having excellent reliability concerning electrical connection can be provided.Type: GrantFiled: September 27, 2004Date of Patent: February 10, 2009Assignee: Panasonic CorporationInventors: Yoshitake Hayashi, Masayoshi Koyama, Satoru Yuhaku, Kazuo Otani, Susumu Matsuoka, Yasushi Taniguchi, Seiichi Nakatani
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Publication number: 20070119617Abstract: A component built-in module of the present invention includes: a first wiring pattern; an electronic component mounted on the first wiring pattern; a second wiring pattern; an electrical insulating sheet with the electrical component built therein, the electrical insulating sheet being disposed between the first wiring pattern and the second wiring pattern; and a via conductor formed in a via hole penetrating through the electrical insulating sheet, the via conductor connecting electrically the first wiring pattern and the second wiring pattern. A side face of the via conductor defines a continuous line in an axis direction of the via conductor. Thus, a component built-in module having excellent reliability concerning electrical connection can be provided.Type: ApplicationFiled: September 27, 2004Publication date: May 31, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Yoshitake Hayashi, Masayoshi Koyama, Satoru Yuhaku, Kazuo Otani, Susumu Matsuoka, Seiichi Nakatani
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Patent number: 7018866Abstract: A circuit component built-in module includes: a first electrical insulating substrate made of a mixture containing an inorganic filler and a thermosetting resin; a plurality of wiring patterns formed at least on a principal surface of the first electrical insulating substrate; a semiconductor chip incorporated in the first electrical insulating substrate and connected electrically with the wiring patterns; and inner vias electrically connecting the plurality of wiring patterns with one another, the inner vias passing through the first electrical insulating substrate. In the circuit component built-in module, the semiconductor chip has a thickness of not less than 30 ?m and not more than 100 ?m, and has a non-wired surface ground, and the circuit component built-in module has a thickness in a range of not less than 80 ?m and not more than 200 ?m.Type: GrantFiled: January 7, 2004Date of Patent: March 28, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuhiro Sugaya, Toshiyuki Asahi, Shingo Komatsu, Yoshiyuki Yamamoto, Seiichi Nakatani, Satoru Yuhaku, Kazuo Ohtani
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Patent number: 6784530Abstract: A circuit component built-in module includes: a first electrical insulating substrate made of a mixture containing an inorganic filler and a thermosetting resin; a plurality of wiring patterns formed at least on a principal surface of the first electrical insulating substrate; a semiconductor chip incorporated in the first electrical insulating substrate and connected electrically with the wiring patterns; and inner vias electrically connecting the plurality of wiring patterns with one another, the inner vias passing through the first electrical insulating substrate. In the circuit component built-in module, the semiconductor chip has a thickness of not less than 30 &mgr;m and not more than 100 &mgr;m, and has a non-wired surface ground, and the circuit component built-in module has a thickness in a range of not less than 80 &mgr;m and not more than 200 &mgr;m.Type: GrantFiled: January 17, 2003Date of Patent: August 31, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuhiro Sugaya, Toshiyuki Asahi, Shingo Komatsu, Yoshiyuki Yamamoto, Seiichi Nakatani, Satoru Yuhaku, Kazuo Ohtani
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Publication number: 20040145044Abstract: A circuit component built-in module includes: a first electrical insulating substrate made of a mixture containing an inorganic filler and a thermosetting resin; a plurality of wiring patterns formed at least on a principal surface of the first electrical insulating substrate; a semiconductor chip incorporated in the first electrical insulating substrate and connected electrically with the wiring patterns; and inner vias electrically connecting the plurality of wiring patterns with one another, the inner vias passing through the first electrical insulating substrate. In the circuit component built-in module, the semiconductor chip has a thickness of not less than 30 &mgr;m and not more than 100 &mgr;m, and has a non-wired surface ground, and the circuit component built-in module has a thickness in a range of not less than 80 &mgr;m and not more than 200 &mgr;m.Type: ApplicationFiled: January 7, 2004Publication date: July 29, 2004Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuhiro Sugaya, Toshiyuki Asahi, Shingo Komatsu, Yoshiyuki Yamamoto, Seiichi Nakatani, Satoru Yuhaku, Kazuo Ohtani
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Patent number: 6723251Abstract: A method for planarizing a circuit board, has a step of fixing a circuit board having wiring layers on both sides to a board having a flat surface through an adhesive layer, wherein said circuit board is pressed from above by a flat member on fixing thereof.Type: GrantFiled: December 18, 2002Date of Patent: April 20, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Minehiro Itagaki, Yoshihiro Tomuro, Satoru Yuhaku, Kazuyoshi Amami
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Patent number: 6703262Abstract: A method for planarizing a circuit board, has a step of fixing a circuit board having wiring layers on both sides to a board having a flat surface through an adhesive layer, wherein said circuit board is pressed from above by a flat member on fixing thereof.Type: GrantFiled: November 19, 1998Date of Patent: March 9, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Minehiro Itagaki, Yoshihiro Tomuro, Satoru Yuhaku, Kazuyoshi Amami
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Publication number: 20030137045Abstract: A circuit component built-in module includes: a first electrical insulating substrate made of a mixture containing an inorganic filler and a thermosetting resin; a plurality of wiring patterns formed at least on a principal surface of the first electrical insulating substrate; a semiconductor chip incorporated in the first electrical insulating substrate and connected electrically with the wiring patterns; and inner vias electrically connecting the plurality of wiring patterns with one another, the inner vias passing through the first electrical insulating substrate. In the circuit component built-in module, the semiconductor chip has a thickness of not less than 30 &mgr;m and not more than 100 &mgr;m, and has a non-wired surface ground, and the circuit component built-in module has a thickness in a range of not less than 80 &mgr;m and not more than 200 &mgr;m.Type: ApplicationFiled: January 17, 2003Publication date: July 24, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuhiro Sugaya, Toshiyuki Asahi, Shingo Komatsu, Yoshiyuki Yamamoto, Seiichi Nakatani, Satoru Yuhaku, Kazuo Ohtani
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Publication number: 20030127725Abstract: The present invention provides a metal wiring board in which metal wiring buried in a surface layer of an electrically insulating substrate is adhered to a carrier sheet covering the metal wiring that can be mechanically detached and that can prevent oxidation of the metal wiring. A semiconductor device that uses this substrate is structured so that a metal terminal electrode buried in an electrically insulating substrate is electrically connected to a protruding electrode on a semiconductor element, the protruding electrode has a structure wherein its tip is flattened by mounting the semiconductor element to the substrate, and the portion where the substrate and the semiconductor element are connected is reinforced by an insulating resin structure and formed into a single unit therewith.Type: ApplicationFiled: December 10, 2002Publication date: July 10, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuhiro Sugaya, Toshiyuki Asahi, Satoru Yuhaku, Seiichi Nakatani
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Publication number: 20030092327Abstract: A method for planarizing a circuit board, has a step of fixing a circuit board having wiring layers on both sides to a board having a flat surface through an adhesive layer, wherein said circuit board is pressed from above by a flat member on fixing thereof.Type: ApplicationFiled: December 18, 2002Publication date: May 15, 2003Inventors: Minehiro Itagaki, Yoshihiro Tomuro, Satoru Yuhaku, Kazuyoshi Amami
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Publication number: 20010029066Abstract: A method for planarizing a circuit board, has a step of fixing a circuit board having wiring layers on both sides to a board having a flat surface through an adhesive layer, wherein said circuit board is pressed from above by a flat member on fixing thereof.Type: ApplicationFiled: November 19, 1998Publication date: October 11, 2001Inventors: MINEHIRO ITAGAKI, YOSHIHIRO TOMURO, SATORU YUHAKU, KAZUYOSHI AMAMI
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Patent number: 6207550Abstract: Disclosed is a method for mounting a semiconductor element, the method requiring no strict flatness for a substrate and being reliable in a semiconductor device produced by mounting a semiconductor element on a circuit substrate. In the multilayer circuit substrate comprising bump electrodes formed of a conductive paste, a conductive adhesive is applied to the top of bump electrodes and then leveled to obtain the end portions on the bump electrodes with a high coplanarity in height. The semiconductor element is mounted on this substrate using a combination of a conductive resin and a sealing resin or an anisotropic conductive sheet. Every top of the bump electrodes after the conductive adhesive is applied has a high coplanarity. The semiconductor element can be mounted with high reliability, on the substrate having such a poor flatness of the electrode face that mounting by a conventional method can not be applied.Type: GrantFiled: June 30, 1998Date of Patent: March 27, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Nobuhiro Hase, Minehiro Itagaki, Yoshifumi Nakamura, Satoru Yuhaku, Hiroaki Takezawa, Yoshihiro Bessho
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Patent number: 5688441Abstract: A conductive paste includes inorganic material powders containing conductive powders and glass powders, an organic vehicle containing an organic binder and an organic solvent, and a metal organic compound.Type: GrantFiled: December 26, 1995Date of Patent: November 18, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Minehiro Itagaki, Yoshihiro Bessho, Satoru Yuhaku, Yasuhiko Hakotani, Kazuhiro Miura, Kazuyuki Okano
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Patent number: 5662755Abstract: A method of making a multi-layered ceramic substrate which includes the steps of laminating a desired number of green sheets each being made of glass ceramics containing at least an organic binder and a solvent and each having a pattern of electrodes formed thereon by the use of an electroconductive paste, to thereby provide a green sheet laminate, The electrodes on opposite surfaces or an entire surface layer of the green sheet laminate are subsequently printed with a paste comprising an inorganic component added with at least an organic binder containing a Zn composition. On each surface of the laminate printed with the paste of the Zn composition, a green sheet made of an inorganic composition incapable of being sintered at a temperature of crystallization of the glass ceramics is then laminated thereby providing a laminate plate which is subsequently fired.Type: GrantFiled: September 11, 1995Date of Patent: September 2, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazuhiro Miura, Yoshihiro Bessho, Satoru Yuhaku, Yasuhiko Hakotani, Minehiro Itagaki, Yoshifumi Nakamura, Akihiko Miyoshi
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Patent number: 5547530Abstract: The method of manufacturing a ceramic substrate having a plurality of bumps of the present invention, includes the steps of: forming a bump forming layer having a plurality of holes therein on at least one of upper and lower faces of a laminated body of green sheets; filling the holes in the bump forming layer with a bump forming paste; sintering the laminated body of the green sheets and the bump forming paste; and forming bumps made of the sintered bump forming paste by removing the bump forming layer.Type: GrantFiled: January 31, 1994Date of Patent: August 20, 1996Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshifumi Nakamura, Yoshihiro Bessho, Satoru Yuhaku, Yasuhiko Hakotani, Minehiro Itagaki, Kazuhiro Miura
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Patent number: 5525402Abstract: The method of manufacturing a ceramic substrate having a plurality of bumps of the present invention, includes the steps of: forming a bump forming layer having a plurality of holes therein on at least one of upper and lower faces of a laminated body of green sheets; filling the holes in the bump forming layer with a bump forming paste; sintering the laminated body of the green sheets and the bump forming layer; and forming bumps made of the sintered bump forming paste by removing the bump forming layer.Type: GrantFiled: February 24, 1995Date of Patent: June 11, 1996Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshifumi Nakamura, Yoshihiro Bessho, Satoru Yuhaku, Yasuhiko Hakotani, Minehiro Itagaki, Kazuhiro Miura
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Patent number: 5503777Abstract: A conductive paste includes inorganic material powders containing conductive powders and glass powders, an organic vehicle containing an organic binder and an organic solvent, and a metal organic compound.Type: GrantFiled: May 10, 1994Date of Patent: April 2, 1996Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Minehiro Itagaki, Yoshihiro Bessho, Satoru Yuhaku, Yasuhiko Hakotani, Kazuhiro Miura, Kazuyuki Okano