Patents by Inventor Satoshi Kudo
Satoshi Kudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6720220Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.Type: GrantFiled: December 23, 2002Date of Patent: April 13, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
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Publication number: 20030148477Abstract: A method for producing phospholipid using transphosphatidylation, which comprises the steps of homogenizing a mixture of a raw material phospholipid, a hydroxyl-containing acceptor, phospholipase D, and water in the absence of an organic solvent to obtain a homogenized mixture; and subjectng said homogenized mixture to the transphosphatidylation reaction at 15° C. to 65° C. The homogenized mixture has a lamellar lyotropic liquid crystal structure. An objective phospholipid can be obtained from the homogenized mixture through transphosphatidylation without using an organic solvent or calcium.Type: ApplicationFiled: February 6, 2003Publication date: August 7, 2003Inventors: Masashi Sakai, Rika Ebina, Hideyuki Yamatoya, Satoshi Kudo
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Publication number: 20030124806Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.Type: ApplicationFiled: December 23, 2002Publication date: July 3, 2003Applicant: Hitachi, Ltd.Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
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Patent number: 6512265Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.Type: GrantFiled: March 27, 2002Date of Patent: January 28, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
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Publication number: 20020098656Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.Type: ApplicationFiled: March 27, 2002Publication date: July 25, 2002Applicant: Hitachi, Ltd.Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
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Patent number: 6410959Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.Type: GrantFiled: September 21, 2001Date of Patent: June 25, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
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Patent number: 6377358Abstract: A method for correcting a recording head is provided to solve the problems of density unevenness in recorded images. The density comparison is made with the reference density for a predetermined unit in the density distribution of an image recorded by the application of n kinds of signals. Then, one of the n kinds of signals which is close to the reference density is selected. The properties of the signal thus selected are transmitted to the recording head together with the correction data, hence correcting density unevenness.Type: GrantFiled: December 24, 1998Date of Patent: April 23, 2002Assignee: Canon Kabushiki KaishaInventors: Kimiyuki Hayasaki, Koji Yamakawa, Tsuyoshi Orikasa, Hiroyuki Kigami, Hisashi Fukai, Takayuki Ono, Masayoshi Okawa, Satoshi Kudo
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Publication number: 20020009867Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.Type: ApplicationFiled: September 21, 2001Publication date: January 24, 2002Applicant: Hitachi, Ltd.Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
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Patent number: 6307231Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.Type: GrantFiled: July 21, 2000Date of Patent: October 23, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
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Patent number: 6168996Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.Type: GrantFiled: August 20, 1998Date of Patent: January 2, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
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Patent number: 6117853Abstract: A cerebration improver having a prominent action for increasing brain glucose level has an effect of improving the cerebration of a subject administered with the improver. The cerebration improver contains as the effective ingredient phosphatidyl-L-serine, or lysophosphatidyl-L-serine produced by eliminating the fatty acid chain at the position .alpha. or .beta. of phosphatidyl-L-serine, or the salts thereof. The phosphatidyl-L-serine has a structural fatty acid chain derived from at least one raw material lecithin selected from the group consisting of soy bean lecithin, rapeseed lecithin or egg yolk lecithin. Using the raw material lecithin as the substrate, phosphatidyl-L-serine can be produced by utilizing transphosphatidylation.Type: GrantFiled: January 12, 1999Date of Patent: September 12, 2000Assignee: Kabushiki Kaisha Yakult HonshaInventors: Masashi Sakai, Hideyuki Yamatoya, Naomi Mizusawa, Satoshi Kudo
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Patent number: 6103346Abstract: To make spherical shape of the terminal end of extruding part of a push-button switch to press a curved contact portion composed of a metal belleville spring and a resin film dome. In addition, the gate injecting mouth 4 for thermoplastic material 3 is opened in the side surface of the extruding part 2 or in the side projection made in a mold to inject the resin material in order to make molding of spherical shape of the terminal end of extruding part 2 of a push-button switch possible. By this structure, the present invention can provide a sheet-like key top having improved clicking touch and preventing break of a contact portion by residual stress.Type: GrantFiled: April 7, 1998Date of Patent: August 15, 2000Assignee: Polymatech Co., Ltd.Inventors: Masaru Nakajo, Kenji Ohgitani, Satoshi Kudo
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Patent number: 5965413Abstract: A process for producing phosphatidylserine having a long chain unsaturated fatty acid in its side chain. In this process, a natural lecithin containing long chain unsaturated fatty acid side chain is used as the starting material. Using the natural lecithin as a substrate for reaction, phospholipase-D is caused to act on the substrate under the presence of serine, whereby phosphatidylserine having a side chain derived from the long chain unsaturated fatty acid can be easily obtained through a single step reaction.Type: GrantFiled: July 3, 1997Date of Patent: October 12, 1999Assignee: Kabushiki Kaisha Yakult HonshaInventors: Masashi Sakai, Hideyuki Yamatoya, Satoshi Kudo
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Patent number: 5900409Abstract: A cerebration improver having a prominent action for increasing brain glucose level has an effect of improving the cerebration of a subject administered with the improver. The cerebration improver contains as the effective ingredient phosphatidyl-L-serine, or lysophosphatidyl-L-serine produced by eliminating the fatty acid chain at the position .alpha. or .beta. of phosphatidyl-L-serine, or the salts thereof. The phosphatidyl-L-serine has a structural fatty acid chain derived from at least one raw material lecithin selected from the group consisting of soy bean lecithin, rapeseed lecithin or egg yolk lecithin. Using the raw material lecithin as the substrate, phosphatidyl-L-serine can be produced by utilizing transphosphatidylation.Type: GrantFiled: November 2, 1995Date of Patent: May 4, 1999Assignee: Kabushiki Kaisha Yakult HonshaInventors: Masashi Sakai, Hideyuki Yamatoya, Naomi Mizusawa, Satoshi Kudo
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Patent number: 5328864Abstract: The present invention relates to a method of manufacturing a semiconductor device. In a semiconductor substrate formed with a first semiconductor region of P-type and a second semiconductor region of N-type and an insulating film formed between and extending into the first and the second semiconductor regions, gate electrodes of a laminate of a polysilicon layer and a silicide layer are formed on the insulating film covering the first and the second semiconductor regions. A gate electrode situated on the first semiconductor region has an end portion facing and spaced from an end portion of a gate electrode situated on the second semiconductor region. A masking layer is formed on the second semiconductor region with an edge of the masking layer falling between the two gate electrodes where the two end portions face each other. The first semiconductor region is doped with an impurity of N-type, thereby forming a third semiconductor region in the first semiconductor region.Type: GrantFiled: May 13, 1991Date of Patent: July 12, 1994Assignee: Hitachi, Ltd.Inventors: Keiichi Yoshizumi, Satoshi Kudo
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Patent number: 5152928Abstract: Surfactant containing one or more of lysophospholipid represented by general formula; ##STR1## [wherein R.sup.1 and R.sup.2 represent hydrogen atom or the acyl residue of fatty acid, but either one of R.sup.1 and R.sup.2 is hydrogen atom, the other being acyl group. X represents an organic group remaining after removing one hydrogen atom of an optional hydroxyl group of polyhydric alcohol therefrom] and the method for producing the same are described.Type: GrantFiled: December 12, 1990Date of Patent: October 6, 1992Assignee: Kabushiki Kaisha Yakult HonshaInventors: Satoshi Kudo, Eriko Nishi
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Patent number: 5037796Abstract: A process for producing a hydrated and cured product of a lime-gypsum-coal ash mixture capable of constituting a high-performance desulfurizing agent, with a high yield and in a simplified manner is provided, which process comprises adding water to a mixture of lime, used desulfurizing agent and coal ash, followed by kneading the resulting mixture, then extruding the resulting kneaded material through a hole of 2 to 10 mm in diameter to obtain bullet-like materials, hydrating and curing said bullet-like materials, followed by drying.Type: GrantFiled: October 10, 1989Date of Patent: August 6, 1991Assignees: The Hokkaido Electric Power Company, Inc., Babcock-Hitachi Kabushiki/KaishaInventors: Satoshi Kudo, Tsutomu Ueno, Tadaaki Mizoguchi, Takanori Kuwahara, Tsukasa Nishimura
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Patent number: 5032537Abstract: The present invention relates to a method of manufacturing a semiconductor device. In a semiconductor substrate formed with a first semiconductor region of P-type and a second semiconductor region of N-type and an insulating film formed between and extending into the first and the second semiconductor regions, gate electrodes of a laminate of a polysilicon layer and a silicide layer are formed on the insulating film covering the first and the second semiconductor regions. A gate electrode situated on the first semiconductor region has an end portion facing and spaced from an end portion of a gate electrode situated on the second semiconductor region. A masking layer is formed on the second semiconductor region with an edge of the masking layer falling between the two gate electrodes where the two end portions face each other. The first semiconductor region is doped with an impurity of N-type, thereby forming a third semiconductor region in the first semiconductor region.Type: GrantFiled: April 16, 1990Date of Patent: July 16, 1991Assignee: Hitachi, Ltd.Inventors: Keiichi Yoshizumi, Satoshi Kudo
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Patent number: 4892837Abstract: Disclosed is a method of producing a bipolar transistor which enables an external base region, an intrinsic base region and an emitter region to be formed in self-alignment with respect to the base electrode. More specifically, the method comprises the steps of side-etching an insulating film formed underneath the base electrode by a wet etching process to provide an undercut portion, depositing polycrystalline silicon so as to extend into the undercut portion by low pressure CVD to thereby fill the undercut portion with the polycrystalline silicon, and subjecting the polycrystalline silicon to thermal oxidation, thereby simultaneously forming a sidewall spacer whereby the base electrode and the emitter electrode are electrically isolated from each other and an oxide film on the emitter forming region, the oxide film having high selectivity in anisotropic etching with respect to the substrate (silicon).Type: GrantFiled: December 2, 1988Date of Patent: January 9, 1990Assignee: Hitachi, Ltd.Inventor: Satoshi Kudo
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Patent number: D490846Type: GrantFiled: September 30, 2003Date of Patent: June 1, 2004Assignee: Canon Kabushiki KaishaInventors: Toru Suzuki, Akira Tsujimoto, Kiyomitsu Kudo, Satoshi Kudo