Patents by Inventor Satoshi Kudo

Satoshi Kudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4892837
    Abstract: Disclosed is a method of producing a bipolar transistor which enables an external base region, an intrinsic base region and an emitter region to be formed in self-alignment with respect to the base electrode. More specifically, the method comprises the steps of side-etching an insulating film formed underneath the base electrode by a wet etching process to provide an undercut portion, depositing polycrystalline silicon so as to extend into the undercut portion by low pressure CVD to thereby fill the undercut portion with the polycrystalline silicon, and subjecting the polycrystalline silicon to thermal oxidation, thereby simultaneously forming a sidewall spacer whereby the base electrode and the emitter electrode are electrically isolated from each other and an oxide film on the emitter forming region, the oxide film having high selectivity in anisotropic etching with respect to the substrate (silicon).
    Type: Grant
    Filed: December 2, 1988
    Date of Patent: January 9, 1990
    Assignee: Hitachi, Ltd.
    Inventor: Satoshi Kudo
  • Patent number: 4808020
    Abstract: In a carriage fixing mechanism for a printing apparatus, engaging openings are formed in a frame disposed at a side portion of the printer and a side portion of a carriage, respectively. The mechanism includes a fixing member. The fixing member includes a first engaging portion to be detachably engaged with the opening of the frame and a second engaging portion to be detachably engaged with the opening of the carriage.
    Type: Grant
    Filed: February 20, 1987
    Date of Patent: February 28, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satoshi Kudo
  • Patent number: 4641419
    Abstract: A process for producing semiconductor devices with a high-performance vertical pnp transistor having a high h.sub.fe and a high f.sub.T, comprising a step for forming an impurity region of a high concentration in a portion of a p-type buried layer and for increasing the concentration in a diffusion layer for isolation, a step for forming an n-type well region that reaches the p-type buried layer and that serves as a base of the vertical pnp transistor, and a step for forming an emitter of the vertical pnp transistor in a portion of said n-type well region, and for forming a collector electrode contact portion of the vertical pnp transistor, said contact portion reaching said impurity region of high concentration, by introducing p-type impurities into a portion of the p-type buried layer that serves as a portion of the collector of the vertical pnp transistor and into the p-type diffusion layer that works as an isolation layer or channel stop layer.
    Type: Grant
    Filed: March 18, 1985
    Date of Patent: February 10, 1987
    Assignee: Hitachi, Ltd.
    Inventor: Satoshi Kudo