Patents by Inventor SATOSHI MICHINAKA

SATOSHI MICHINAKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955559
    Abstract: Provided are a thin film transistor, a display device, and a thin film transistor manufacturing method, in which variation in characteristics is small. The present invention is provided with: a gate electrode formed on a substrate; a gate insulation film formed so as to cover the gate electrode; a semiconductor layer which is formed on the upper side of the gate insulation film and which includes a polysilicon layer disposed, in a plan view, inside a region defined by the gate electrode; an etching stopper layer disposed on the upper side of the polysilicon layer; and a source electrode and a drain electrode provided on the semiconductor layer so as to be separated from each other, wherein the polysilicon layer has first and second regions which are not covered with the etching stopper layer, and a part of the source electrode exists above the first region and a part of the drain electrode exists above the second region.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: April 9, 2024
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: Yoshiaki Matsushima, Shigeru Ishida, Ryohei Takakura, Satoru Utsugi, Nobutake Nodera, Takao Matsumoto, Satoshi Michinaka
  • Publication number: 20210391475
    Abstract: Provided are a thin film transistor, a display device, and a thin film transistor manufacturing method, in which variation in characteristics is small. The present invention is provided with: a gate electrode formed on a substrate; a gate insulation film formed so as to cover the gate electrode; a semiconductor layer which is formed on the upper side of the gate insulation film and which includes a polysilicon layer disposed, in a plan view, inside a region defined by the gate electrode; an etching stopper layer disposed on the upper side of the polysilicon layer; and a source electrode and a drain electrode provided on the semiconductor layer so as to be separated from each other, wherein the polysilicon layer has first and second regions which are not covered with the etching stopper layer, and a part of the source electrode exists above the first region and a part of the drain electrode exists above the second region.
    Type: Application
    Filed: August 27, 2021
    Publication date: December 16, 2021
    Inventors: YOSHIAKI MATSUSHIMA, SHIGERU ISHIDA, RYOHEI TAKAKURA, SATORU UTSUGI, NOBUTAKE NODERA, TAKAO MATSUMOTO, SATOSHI MICHINAKA
  • Publication number: 20200402823
    Abstract: A laser annealing apparatus 100 includes a laser irradiation device 10 to emit a plurality of laser beams LB toward an irradiation region R1 of a stage 20, the laser irradiation device including: a laser device to emit a laser beam LA; and a convergence unit that includes a microlens array 34 having a plurality of microlenses 34A arranged in m rows and n columns and a mask 32 having a plurality of apertures 32A, the convergence unit 30 receiving the laser beam from the laser device to form respective convergence points of the plurality of laser beams within the irradiation region R1. The plurality of laser beams are p rows and q columns of laser beams formed by p rows and q columns of microlenses (p<m or q<n) among the m rows and n columns of microlenses.
    Type: Application
    Filed: March 7, 2018
    Publication date: December 24, 2020
    Applicant: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: NOBUTAKE NODERA, TOMOHIRO INOUE, SHINJI KOIWA, SATOSHI MICHINAKA
  • Patent number: 10770483
    Abstract: A thin film transistor includes: a gate electrode supported on a substrate; a gate insulating layer that covers the gate electrode; an oxide semiconductor layer provided on the gate insulating layer and having a crystalline region, the crystalline region including a first region, a second region, and a channel region located between the first region and the second region, wherein the channel region, the first region and the second region overlap with the gate electrode with the gate insulating layer interposed therebetween; a protection insulating layer arranged on the oxide semiconductor layer so that the channel region is covered and the first region and the second region are exposed; a source electrode electrically connected to the first region; and a drain electrode electrically connected to the second region, wherein a crystallinity of the channel region is different from a crystallinity of the first region and the second region.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: September 8, 2020
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: Yuta Sugawara, Satoshi Michinaka, Nobutake Nodera, Takao Matsumoto
  • Publication number: 20200006396
    Abstract: A thin film transistor includes: a gate electrode supported on a substrate; a gate insulating layer that covers the gate electrode; an oxide semiconductor layer provided on the gate insulating layer and having a crystalline region, the crystalline region including a first region, a second region, and a channel region located between the first region and the second region, wherein the channel region, the first region and the second region overlap with the gate electrode with the gate insulating layer interposed therebetween; a protection insulating layer arranged on the oxide semiconductor layer so that the channel region is covered and the first region and the second region are exposed; a source electrode electrically connected to the first region; and a drain electrode electrically connected to the second region, wherein a crystallinity of the channel region is different from a crystallinity of the first region and the second region.
    Type: Application
    Filed: April 2, 2019
    Publication date: January 2, 2020
    Inventors: YUTA SUGAWARA, SATOSHI MICHINAKA, NOBUTAKE NODERA, TAKAO MATSUMOTO
  • Publication number: 20190140102
    Abstract: Provided are a thin film transistor, a display device, and a thin film transistor manufacturing method, in which variation in characteristics is small. The present invention is provided with: a gate electrode formed on a substrate; a gate insulation film formed so as to cover the gate electrode; a semiconductor layer which is formed on the upper side of the gate insulation film and which includes a polysilicon layer disposed, in a plan view, inside a region defined by the gate electrode; an etching stopper layer disposed on the upper side of the polysilicon layer; and a source electrode and a drain electrode provided on the semiconductor layer so as to be separated from each other, wherein the polysilicon layer has first and second regions which are not covered with the etching stopper layer, and a part of the source electrode exists above the first region and a part of the drain electrode exists above the second region.
    Type: Application
    Filed: April 25, 2016
    Publication date: May 9, 2019
    Applicant: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: YOSHIAKI MATSUSHIMA, SHIGERU ISHIDA, RYOHEI TAKAKURA, SATORU UTSUGI, NOBUTAKE NODERA, TAKAO MATSUMOTO, SATOSHI MICHINAKA