Patents by Inventor Satoshi Muramatsu

Satoshi Muramatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11908628
    Abstract: A multilayer ceramic capacitor includes an external electrode including an underlying electrode layer, a lower plating layer on the underlying electrode layer at a first end surface and a second end surface, and an upper plating layer on the lower plating layer. The underlying electrode layer is a thin film electrode including at least one selected from Ni, Cr, Cu, and Ti. The lower plating layer is a Cu plating layer including a lower layer region located closer to the multilayer body and an upper layer region located between the lower layer region and the upper plating layer, and the Cu plating layer in the lower layer region has a metal grain diameter smaller than that of the Cu plating layer located in the upper layer region.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: February 20, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Muramatsu, Ken Tominaga
  • Publication number: 20240045372
    Abstract: An imaging system includes a housing, a developer roller that transfers developer to an image carrier at a development region, a developer regulator to limit a thickness of the developer carried on the developer roller, and an air passage that extends outside a development chamber. The air passage has an inlet to draw an airflow, and an outlet located between the developer regulator and the development region. The air passage has a cross section orthogonal to a direction of the airflow from the inlet to the outlet. In the cross section taken at the narrowest position where the air passage is the narrowest, a width in a width direction parallel to a rotational axis of the developer roller is greater than a thickness that is perpendicular to the width direction.
    Type: Application
    Filed: August 27, 2020
    Publication date: February 8, 2024
    Inventors: Tadao MORI, Naoya IWATA, Satoshi MURAMATSU
  • Publication number: 20230352242
    Abstract: A multilayer ceramic capacitor includes a laminate including dielectric layers and internal electrode layers, and first and second external electrodes on surfaces of the laminate. The laminate includes first and second main surfaces oppose each other in a lamination direction, first and second side surfaces oppose each other in a length direction perpendicular or substantially perpendicular to the lamination direction, and third and fourth side surfaces oppose each other in a width direction perpendicular or substantially perpendicular to the lamination direction and the length direction. A length ratio EB1/EA1 of the first external electrode wrapping around to main surfaces of the laminate is about 0 or more and about 0.5 or less. A length ratio EB2/EA2 of the second external electrode wrapping around to the main surfaces of the laminate is about 0 or more and about 0.5 or less.
    Type: Application
    Filed: June 22, 2023
    Publication date: November 2, 2023
    Inventors: Suguru NAKANO, Satoshi MURAMATSU, Risa HOJO, Yoshiyuki NOMURA
  • Patent number: 11798742
    Abstract: A mounting structure of a multilayer ceramic capacitor includes a substrate, and a multilayer ceramic capacitor connected to the substrate and including a laminate including dielectric layers and internal electrode layers, and external electrodes on main surfaces of the laminate. The laminate further includes first, second, third, and fourth via conductors connecting the internal electrode layers and the external electrodes. The external electrodes include first, second, third, and fourth external electrodes, each connected to respective end surfaces of the via conductor. Each of the external electrodes does not extend to the side surfaces of the laminate. A ratio W/L of a dimension W in the width direction of the multilayer ceramic capacitor to a dimension L in the length direction of the multilayer ceramic capacitor is about 0.85 or more and about 1 or less.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: October 24, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Suguru Nakano, Satoshi Muramatsu, Risa Hojo, Yoshiyuki Nomura
  • Patent number: 11791102
    Abstract: A multilayer ceramic capacitor has a relationship of about 10°??1?about 50° and a relationship of about 10°??2?about 50°, where ?1 denotes an angle between a first end surface and a perpendicular extending from a side of a first main surface at a point of intersection of the first main surface and the first end surface, and ?2 denotes an angle between a second end surface and a perpendicular extending from a side of the first main surface at a point of intersection of the first main surface and the second end surface.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: October 17, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Suguru Nakano, Risa Hojo, Akira Tanaka, Toru Nishikawa, Satoshi Muramatsu
  • Publication number: 20230307186
    Abstract: A multilayer ceramic capacitor includes a ceramic body including ceramic layers, first internal electrodes, and second internal electrodes laminated in a height direction, a first external electrode on at least part of a first end surface and on part of a first main surface and not on a second main surface, the first external electrode being electrically connected to the first internal electrodes, a second external electrode on at least part of a second end surface and on part of the first main surface and is not on the second main surface, the second external electrode being electrically connected to the second internal electrodes, at least two penetration portions penetrating the ceramic body between the first and second main surfaces, and a reinforcing layer on at least part of the second main surface, the reinforcing layer covering the at least two penetration portions exposed from the ceramic body.
    Type: Application
    Filed: March 16, 2023
    Publication date: September 28, 2023
    Inventors: Kosuke ONISHI, Satoshi MURAMATSU, Yukie WATANABE, Ryo NISHIMURA
  • Publication number: 20230298818
    Abstract: A multilayer ceramic capacitor includes a multilayer body in which a dimension in a width direction >a dimension in a length direction >a dimension in a height direction is satisfied. A dimension in the length direction of each of lateral surface exposed portions is about 10% or more and about 44% or less with respect to the dimension in the length direction. A dimension of the external electrode in the length direction is about 17% or more and about 48% or less with respect to the dimension in the length direction.
    Type: Application
    Filed: February 3, 2023
    Publication date: September 21, 2023
    Inventors: Kotaro KISHI, Satoshi MURAMATSU
  • Patent number: 11754949
    Abstract: An imaging system includes a developing chamber, a first conveyance path, a second conveyance path, a first air passage and a second air passage. A developing roller located in the developing chamber carries a developer to a developing region where the developing roller is closest to an image carrier. A first stirring-conveying portion is located in the first conveyance path adjacent the developing roller to supply the developer to the developing roller. A second stirring-conveying portion is located in the second conveyance path adjacent the first conveyance path to circulate the developer between the second conveyance path and the first conveyance path. The first air passage has an inlet coupled to the developing chamber and an outlet coupled to the second conveyance path, and the second air passage has an inlet coupled to the second conveyance path and an outlet coupled to the developing chamber.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: September 12, 2023
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Satoshi Muramatsu
  • Publication number: 20230260710
    Abstract: A multilayer ceramic capacitor includes a capacitive element including ceramic layers, first and second internal electrodes, first and second main surfaces, end surfaces, and side surfaces. A portion of the first and second side surfaces, and a portion of the first and second end surfaces include SiO2 films. The SiO2 films on the first and second side surfaces cover the first and second internal electrodes, respectively exposed on the first and second side surfaces. First and second external electrodes are respectively provided at least on an outer surface of the first end surface on which the SiO2 film is not provided and an outer surface of the SiO2 film provided on the first end surface and on at least on an outer surface of the second end surface on which the SiO2 film is not provided and an outer surface of the SiO2 film provided on the second end surface.
    Type: Application
    Filed: January 6, 2023
    Publication date: August 17, 2023
    Inventor: Satoshi MURAMATSU
  • Publication number: 20230260711
    Abstract: A multilayer ceramic capacitor includes ceramic layers, internal electrodes, opposed principal surfaces, opposed end surfaces, and opposed side surfaces, and external electrodes on a surface of the capacitive body. The external electrodes include Ni and Sn, and have a C-shape on the end surface of the capacitive body and the principal surfaces when a section parallel to the side surfaces is viewed, the C-shape external electrodes include a first region and a second region completely surrounding the first region, an area of Sn is greater than or equal to about 90% with respect to a total of an area of Ni and the area of Sn, and in the first region, the area of Sn is less than about 90% with respect to the total of the area of Ni and the area of Sn appearing in a measurement region.
    Type: Application
    Filed: February 1, 2023
    Publication date: August 17, 2023
    Inventor: Satoshi MURAMATSU
  • Patent number: 11728096
    Abstract: A multilayer ceramic capacitor includes a laminate including dielectric layers and internal electrode layers, and external electrodes on surfaces of the laminate. A silane coupling agent layer is on at least a mounting surface among surfaces of the laminate. The silane coupling agent layer is made of a fluorine-based silane coupling agent, and a silane coupling agent concentration on the mounting surface is about 0.1 or higher and about 365 or lower and is higher than a silane coupling agent concentration on a counter surface opposing the mounting surface, or the silane coupling agent layer is made of a carbon-based silane coupling agent, and a silane coupling agent concentration on the mounting surface is about 0.91 or higher and about 38.10 or lower and is higher than a silane coupling agent concentration on a counter surface opposing the mounting surface.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: August 15, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Suguru Nakano, Satoshi Muramatsu, Risa Hojo, Yoshiyuki Nomura
  • Publication number: 20230253160
    Abstract: A multilayer ceramic capacitor includes a stacked body and external electrodes. The stacked body includes stacked dielectric layers and internal electrodes. The external electrodes are disposed on lateral surfaces of the stacked body and are connected to the internal electrodes. A ratio of min to max is not less than about 36% and not more than about 90%, where A1, A2, A3, and A4 respectively denote the surface areas of first, second, third, and fourth external electrodes that are located on the first or second main surface of the stacked body.
    Type: Application
    Filed: March 24, 2023
    Publication date: August 10, 2023
    Inventor: Satoshi MURAMATSU
  • Publication number: 20230230774
    Abstract: A multilayer ceramic capacitor includes a stacked body and external electrodes. The stacked body includes stacked dielectric layers and internal electrodes. The external electrodes are disposed on lateral surfaces of the stacked body and are connected to the internal electrodes. The dielectric layers include outer layer portions and an effective layer portion. Each outer layer portion is adjacent to a corresponding main surface of the stacked body. Each outer layer portion is a dielectric layer located between a corresponding main surface and an internal electrode closest to the main surface. A ratio of a dimension of the effective layer portion in a stacking direction to a dimension of the stacked body in the stacking direction is not less than about 53% and not more than about 83%.
    Type: Application
    Filed: March 29, 2023
    Publication date: July 20, 2023
    Inventor: Satoshi MURAMATSU
  • Publication number: 20230154685
    Abstract: A multilayer ceramic capacitor includes a multilayer body having a dimensional relationship of the dimension in the width direction is greater than the dimension in the length direction which is greater than the dimension in the height direction. The dimension in the width direction of a third surface portion of a first external electrode is smaller than the dimension in the width direction of a first surface portion. The dimension in the width direction of an eighth surface portion of a second external electrode is smaller than the dimension in the width direction of a sixth surface portion. The dimensions in the height direction of a fourth surface portion and a fifth surface portion of the first external electrode are smaller than the dimension in the height direction of the first surface portion.
    Type: Application
    Filed: October 27, 2022
    Publication date: May 18, 2023
    Inventors: Kotaro KISHI, Satoshi MURAMATSU
  • Patent number: 11646162
    Abstract: A multilayer ceramic capacitor includes a stacked body and external electrodes. The stacked body includes stacked dielectric layers and internal electrodes. The external electrodes are disposed on lateral surfaces of the stacked body and are connected to the internal electrodes. The dielectric layers include outer layer portions and an effective layer portion. Each outer layer portion is adjacent to a corresponding main surface of the stacked body. Each outer layer portion is a dielectric layer located between a corresponding main surface and an internal electrode closest to the main surface. A ratio of a dimension of the effective layer portion in a stacking direction to a dimension of the stacked body in the stacking direction is not less than about 53% and not more than about 83%.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: May 9, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Satoshi Muramatsu
  • Patent number: 11646159
    Abstract: A multilayer ceramic capacitor includes a stacked body and external electrodes. The stacked body includes stacked dielectric layers and internal electrodes. The external electrodes are disposed on lateral surfaces of the stacked body and are connected to the internal electrodes. A ratio of min to max is not less than about 36% and not more than about 90%, where A1, A2, A3, and A4 respectively denote the surface areas of first, second, third, and fourth external electrodes that are located on the first or second main surface of the stacked body.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: May 9, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Satoshi Muramatsu
  • Publication number: 20230133747
    Abstract: A mounting structure of a multilayer ceramic capacitor includes a substrate, and a multilayer ceramic capacitor connected to the substrate and including a laminate including dielectric layers and internal electrode layers, and external electrodes on main surfaces of the laminate. The laminate further includes first, second, third, and fourth via conductors connecting the internal electrode layers and the external electrodes. The external electrodes include first, second, third, and fourth external electrodes, each connected to respective end surfaces of the via conductor. Each of the external electrodes does not extend to the side surfaces of the laminate. A ratio W/L of a dimension W in the width direction of the multilayer ceramic capacitor to a dimension L in the length direction of the multilayer ceramic capacitor is about 0.85 or more and about 1 or less.
    Type: Application
    Filed: January 3, 2023
    Publication date: May 4, 2023
    Inventors: Suguru NAKANO, Satoshi MURAMATSU, Risa HOJO, Yoshiyuki NOMURA
  • Publication number: 20230095128
    Abstract: A multilayer ceramic capacitor includes an external electrode including an underlying electrode layer, a lower plating layer on the underlying electrode layer at a first end surface and a second end surface, and an upper plating layer on the lower plating layer. The underlying electrode layer is a thin film electrode including at least one selected from Ni, Cr, Cu, and Ti. The lower plating layer is a Cu plating layer including a lower layer region located closer to the multilayer body and an upper layer region located between the lower layer region and the upper plating layer, and the Cu plating layer in the lower layer region has a metal grain diameter smaller than that of the Cu plating layer located in the upper layer region.
    Type: Application
    Filed: December 6, 2022
    Publication date: March 30, 2023
    Inventors: Satoshi MURAMATSU, Ken TOMINAGA
  • Publication number: 20230083171
    Abstract: In a multilayer ceramic capacitor, when a dimension in a length direction between a first end surface and a second end surface of a multilayer body is defined as l, a dimension in a width direction between a first lateral surface and a second lateral surface of the multilayer body is defined as w, and a dimension in a height direction between a first main surface and a second main surface of the multilayer body is defined as t, a dimensional relationship of w>l>t is satisfied, and a fourth surface portion and a fifth surface portion of the first external electrode, and a ninth surface portion and a tenth surface portion of the second external electrode each include an opening portion at which a surface of the multilayer body is exposed.
    Type: Application
    Filed: August 26, 2022
    Publication date: March 16, 2023
    Inventors: Kotaro KISHI, Satoshi MURAMATSU
  • Patent number: 11600440
    Abstract: A multilayer ceramic capacitor includes: a laminate including dielectric layers and internal electrode layers; and external electrodes on the main surfaces of the laminate. The laminate further includes a first via conductor, a second via conductor, a third via conductor, and a fourth via conductor that connect the internal electrode layers and the external electrodes. The external electrodes include first external electrodes, second external electrodes, third external electrodes, and fourth external electrodes, each connected to the respective end surfaces of the via conductor. Each of the external electrodes does not extend to the side surfaces of the laminate. A ratio W/L of a dimension W in the width direction of the multilayer ceramic capacitor to a dimension L in the length direction of the multilayer ceramic capacitor is about 0.85 or more and about 1 or less. The dimension L in the length direction of the multilayer ceramic capacitor is about 750 ?m or smaller.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: March 7, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Suguru Nakano, Satoshi Muramatsu, Risa Hojo, Yoshiyuki Nomura