Patents by Inventor Satoshi Nagashima

Satoshi Nagashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10002880
    Abstract: According to one embodiment, an insulating layer is provided above a word line contact region portion. An upper surface of the insulating layer is at a height higher than an uppermost conductive layer. A first cover film is provided between the word line contact region portion and the insulating layer. A second cover film included in a first separation portion covers a side surface along a first direction of the insulating layer and a side surface along the first direction of the word line contact region portion. A third cover film is provided on the uppermost conductive layer. The third cover film covers a side surface along a second direction of the insulating layer. The first, second, and third cover films are of materials different from a material of the insulating layer.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: June 19, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Satoshi Nagashima
  • Patent number: 9966381
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a first conductive film provided on a first region of the first insulating film, a second conductive film provided on a second region of the first insulating film, a first stacked body provided on the first conductive film, a second stacked body provided on the second conductive film, a first semiconductor pillar, and two conductive pillars. In the first stacked body, a second insulating film and an electrode film are stacked alternately. In the second stacked body, a third insulating film and a first film are stacked alternately. The two conductive pillars extend in the first direction through the second stacked body, are separated from the second conductive film, sandwich the second conductive film, and are connected at a bottom ends of the second conductive pillars to the semiconductor substrate.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: May 8, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Fumitaka Arai, Tatsuya Kato, Satoshi Nagashima, Katsuyuki Sekine, Yuta Watanabe, Keisuke Kikutani, Atsushi Murakoshi
  • Publication number: 20180097011
    Abstract: A semiconductor memory device according to one embodiment, includes a first electrode film, a plurality of semiconductor members, and a charge storage member. The first electrode film includes three or more first portions and a second portion connecting the first portions to each other. The first portions extend in a first direction and are arranged along a second direction that intersects with the first direction. The plurality of semiconductor members are arranged along the first direction between the first portions and extending in a third direction. The third direction intersects with a plane containing the first direction and the second direction. The charge storage member is disposed between each of the semiconductor members and each of the first portions. The second portion is disposed between the semiconductor members.
    Type: Application
    Filed: November 21, 2017
    Publication date: April 5, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Koichi Sakata, Yuta Watanabe, Keisuke Kikutani, Satoshi Nagashima, Fumitaka Arai, Toshiyuki Iwamoto
  • Publication number: 20180083018
    Abstract: A semiconductor memory device includes a semiconductor substrate, a stepped structure including a stepped part in which a plurality of first insulating layers and conductive layers are alternately stacked on a main surface of the semiconductor substrate, the conductive layers including first, second, and third conductive layers, a second insulating layer which covers the stepped structure, a first contact interconnection which penetrates the second insulating layer and the first conductive layer in a thickness direction of the semiconductor substrate and is electrically connected to the second conductive layer, and a second contact interconnection which penetrates the second insulating layer and the second conductive layer in the thickness direction of the semiconductor substrate and is electrically connected to the third conductive layer.
    Type: Application
    Filed: August 28, 2017
    Publication date: March 22, 2018
    Inventors: Shigehiro YAMAKITA, Yoshiaki FUKUZUMI, Wataru SAKAMOTO, Satoshi NAGASHIMA
  • Publication number: 20180006051
    Abstract: A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other.
    Type: Application
    Filed: September 15, 2017
    Publication date: January 4, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Satoshi NAGASHIMA, Tatsuya KATO
  • Patent number: 9847342
    Abstract: A semiconductor memory device includes a first structural body, a second structural body and interconnections. The first and the second structural bodies are separated in a first direction and extend in a second direction. The interconnections are provided between the first structural body and the second structural body, extend in the second direction, and are separated from each other along a third direction. The first and the second structural bodies each includes an insulating member, a column-shaped body and an insulating film. The insulating member and the column-shaped body are disposed in an alternating manner along the second direction and extend in the third direction. The insulating members of the first and second structural bodies make contact with the interconnections.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: December 19, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Nagashima, Katsumi Yamamoto, Kohei Sakaike, Tatsuya Kato, Keisuke Kikutani, Fumitaka Arai, Atsushi Murakoshi, Shunichi Takeuchi, Katsuyuki Sekine
  • Patent number: 9837434
    Abstract: A semiconductor memory device according to one embodiment, includes a first electrode film, a plurality of semiconductor members, and a charge storage member. The first electrode film includes three or more first portions and a second portion connecting the first portions to each other. The first portions extend in a first direction and are arranged along a second direction that intersects with the first direction. The plurality of semiconductor members are arranged along the first direction between the first portions and extending in a third direction. The third direction intersects with a plane containing the first direction and the second direction. The charge storage member is disposed between each of the semiconductor members and each of the first portions. The second portion is disposed between the semiconductor members.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: December 5, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Koichi Sakata, Yuta Watanabe, Keisuke Kikutani, Satoshi Nagashima, Fumitaka Arai, Toshiyuki Iwamoto
  • Publication number: 20170271348
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a first conductive film provided on a first region of the first insulating film, a second conductive film provided on a second region of the first insulating film, a first stacked body provided on the first conductive film, a second stacked body provided on the second conductive film, a first semiconductor pillar, and two conductive pillars. In the first stacked body, a second insulating film and an electrode film are stacked alternately. In the second stacked body, a third insulating film and a first film are stacked alternately. The two conductive pillars extend in the first direction through the second stacked body, are separated from the second conductive film, sandwich the second conductive film, and are connected at a bottom ends of the second conductive pillars to the semiconductor substrate.
    Type: Application
    Filed: September 16, 2016
    Publication date: September 21, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Fumitaka ARAI, Tatsuya KATO, Satoshi NAGASHIMA, Katsuyuki SEKINE, Yuta WATANABE, Keisuke KIKUTANI, Atsushi MURAKOSHI
  • Publication number: 20170263637
    Abstract: A semiconductor memory device according to one embodiment, includes a first electrode film, a plurality of semiconductor members, and a charge storage member. The first electrode film includes three or more first portions and a second portion connecting the first portions to each other. The first portions extend in a first direction and are arranged along a second direction that intersects with the first direction. The plurality of semiconductor members are arranged along the first direction between the first portions and extending in a third direction. The third direction intersects with a plane containing the first direction and the second direction. The charge storage member is disposed between each of the semiconductor members and each of the first portions. The second portion is disposed between the semiconductor members.
    Type: Application
    Filed: September 16, 2016
    Publication date: September 14, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koichi SAKATA, Yuta WATANABE, Keisuke KlKUTANI, Satoshi NAGASHIMA, Fumitaka ARAI, Toshiyuki IWAMOTO
  • Publication number: 20170263619
    Abstract: A semiconductor memory device includes a first structural body, a second structural body and interconnections. The first and the second structural bodies are separated in a first direction and extend in a second direction. The interconnections are provided between the first structural body and the second structural body, extend in the second direction, and are separated from each other along a third direction. The first and the second structural bodies each includes an insulating member, a column-shaped body and an insulating film. The insulating member and the column-shaped body are disposed in an alternating manner along the second direction and extend in the third direction. The insulating members of the first and second structural bodies make contact with the interconnections.
    Type: Application
    Filed: September 16, 2016
    Publication date: September 14, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Satoshi NAGASHIMA, Katsumi YAMAMOTO, Kohei SAKAIKE, Tatsuya KATO, Keisuke KlKUTANI, Fumitaka ARAI, Atsushi MURAKOSHI, Shunichi TAKEUCHI, Katsuyuki SEKINE
  • Publication number: 20170263615
    Abstract: A semiconductor memory device according to an embodiment, includes a first semiconductor member, a second semiconductor member, an insulating member, a plurality of electrode films, a first electrode, and a second electrode. The first semiconductor member and the second semiconductor member are separated in a first direction and extending in a second direction. The second direction crosses the first direction. The insulating member is provided between the first semiconductor member and the second semiconductor member. The plurality of electrode films are arranged to be separated from each other along the second direction. Each of the electrode films surrounds the first semiconductor member, the second semiconductor member, and the insulating member when viewed from the second direction. The first electrode is provided between the first semiconductor member and the electrode film. The second electrode is provided between the second semiconductor member and the electrode film.
    Type: Application
    Filed: March 3, 2017
    Publication date: September 14, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kohei SAKAIKE, Toshiyuki IWAMOTO, Tatsuya KATO, Keisuke KlKUTANI, Fumitaka ARAI, Satoshi NAGASHIMA, Koichi SAKATA, Yuta WATANABE
  • Patent number: 9735167
    Abstract: A semiconductor memory device according to one embodiment, includes a plurality of first interconnects extending in a first direction and arrayed along a second direction crossing the first direction, a plurality of semiconductor pillars arrayed in a row along the first direction in each of spaces among the first interconnects and extending in a third direction crossing the first direction and the second direction, a first electrode disposed between one of the semiconductor pillars and one of the first interconnects, a first insulating film disposed between the first electrode and one of the first interconnects, a first insulating member disposed between the semiconductor pillars in the first direction and extending in the third direction and opposed the first interconnects not via the first insulating film.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: August 15, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuya Kato, Fumitaka Arai, Satoshi Nagashima, Katsuyuki Sekine, Yuta Watanabe, Keisuke Kikutani, Atsushi Murakoshi
  • Patent number: 9653314
    Abstract: A semiconductor device according to the present embodiment includes a plurality of wires. A plurality of wire drawing pads are provided correspondingly to the wires and electrically connecting a plurality of contacts to the wires, respectively. First space portions widen toward a first direction from the wires to the wire drawing pads and are located between adjacent ones of the wire drawing pads in a connection region between the wires and the wire drawing pads. Second space portions are provided at edge portions of the wire drawing pads. Air gaps or insulating layers are provided in the first space portions and the second space portions.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: May 16, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoshi Nagashima, Koichi Matsuno, Takashi Sugihara, Hiroaki Naito
  • Patent number: 9620515
    Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor pillar extending in a first direction in a first region. The semiconductor memory device also includes a first electrode film provided on a side of the semiconductor pillar and extending in a second direction different from the first direction in the first region and in a second region adjacent to the first region in the second direction. The semiconductor memory device also includes a second electrode film provided between the semiconductor pillar and the first electrode film in the first region. Film thickness in the first direction of the first electrode film in the first region is smaller than film thickness in the first direction of the first electrode film in the second region.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: April 11, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Nagashima, Tatsuya Kato, Keisuke Kikutani
  • Patent number: 9548310
    Abstract: According to an embodiment, a semiconductor device includes a semiconductor substrate, a first region that is provided on the semiconductor substrate and has a line-and-space pattern extending in a first direction, and a second region that is provided adjacent to the first region on the semiconductor substrate and has a dummy pattern. The surface area per unit area of the second region is greater than the surface area per unit area of the first region.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: January 17, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hajime Kaneko, Satoshi Nagashima
  • Publication number: 20170012050
    Abstract: A semiconductor memory device according to one embodiment, includes a plurality of first interconnects extending in a first direction and arrayed along a second direction crossing the first direction, a plurality of semiconductor pillars arrayed in a row along the first direction in each of spaces among the first interconnects and extending in a third direction crossing the first direction and the second direction, a first electrode disposed between one of the semiconductor pillars and one of the first interconnects, a first insulating film disposed between the first electrode and one of the first interconnects, a first insulating member disposed between the semiconductor pillars in the first direction and extending in the third direction and opposed the first interconnects not via the first insulating film.
    Type: Application
    Filed: August 31, 2015
    Publication date: January 12, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuya KATO, Fumitaka ARAI, Satoshi NAGASHIMA, Katsuyuki SEKINE, Yuta WATANABE, Keisuke KIKUTANI, Atsushi MURAKOSHI
  • Patent number: 9543310
    Abstract: A semiconductor storage device according to an embodiment of the invention includes a semiconductor substrate and a plurality of memory cells on the semiconductor substrate. A first film is provided above the memory cells to form air gaps above a memory string in which the memory cells are connected in series.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: January 10, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoshi Nagashima, Takehiro Kondoh
  • Patent number: 9530782
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a memory element including a first gate electrode having a first thickness disposed on a first insulation film on the semiconductor substrate, and a first peripheral element other than a memory element including a second gate electrode having a second thickness disposed on a second insulation film on the semiconductor substrate. The first gate electrode and second gate electrode comprise a plurality of film layers, and the configuration of the film layers are different as between the first gate electrode of the memory element and the second gate electrode of the peripheral element, and the first thickness is different from the second thickness.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: December 27, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazunari Toyonaga, Shoichi Watanabe, Karin Takayama, Shotaro Murata, Satoshi Nagashima
  • Publication number: 20160336336
    Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor pillar extending in a first direction in a first region. The semiconductor memory device also includes a first electrode film provided on a side of the semiconductor pillar and extending in a second direction different from the first direction in the first region and in a second region adjacent to the first region in the second direction. The semiconductor memory device also includes a second electrode film provided between the semiconductor pillar and the first electrode film in the first region. Film thickness in the first direction of the first electrode film in the first region is smaller than film thickness in the first direction of the first electrode film in the second region.
    Type: Application
    Filed: August 6, 2015
    Publication date: November 17, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Satoshi NAGASHIMA, Tatsuya KATO, Keisuke KIKUTANI
  • Patent number: 9466606
    Abstract: A semiconductor storage device according to an embodiment comprises stacks comprising insulating films and first wires that are alternately stacked. Semiconductor parts are provided in the stacks. The longitudinal direction of the semiconductor parts is a stacking direction of the insulating films and the first wires. Charge accumulation layers are provided between the first wires and the semiconductor parts and a plurality of the charge accumulation layers are provided corresponding to one of the semiconductor parts in a cross-section in a direction perpendicular to the longitudinal direction of the semiconductor parts. A width of first side surfaces of the semiconductor parts on which the charge accumulation layers are provided is larger at bottom ends of the semiconductor parts than at top ends of the semiconductor parts.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: October 11, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Satoshi Nagashima