Patents by Inventor Satoshi Shinohara

Satoshi Shinohara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230275159
    Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.
    Type: Application
    Filed: February 9, 2023
    Publication date: August 31, 2023
    Inventors: Shunpei YAMAZAKI, Satoshi SHINOHARA
  • Publication number: 20230256742
    Abstract: A liquid droplet-forming device is provided, including: a liquid chamber; a discharge hole configured to discharge a raw material liquid in the liquid chamber in a form of liquid droplets; sealed space-forming means; and at least two flow paths, in which the sealed space-forming means is capable of forming a sealed space communicating with the liquid chamber through the discharge hole on a side opposite to the liquid chamber of the discharge hole, and the at least two flow paths communicate with each other through the sealed space.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 17, 2023
    Inventors: Hisayoshi OHSHIMA, Yuichi SATO, Shinji AOKI, Satoshi SHINOHARA, Shuusuke IWATA
  • Patent number: 11590457
    Abstract: A manufacturing method for a separation membrane element is a manufacturing method for a spiral-wound type separation membrane element including a perforated hollow tube and a laminated body that includes a separation membrane and is wound around the hollow tube. The manufacturing method includes pressing a press member against a portion of the laminated body that is wound around the hollow tube. The pressing presses the press member to satisfy respective relations defined by formulas (1) and (2): 0.1×Ps1?Pe??(1), and 0.1×Ps2?Pe??(2).
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: February 28, 2023
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Satoshi Shinohara, Hisaaki Miyamoto
  • Patent number: 11588058
    Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: February 21, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Shinohara
  • Patent number: 11547953
    Abstract: A method of producing an extract of an animal-derived or plant-derived biological material includes: extracting a component in the biological material using liquefied dimethyl ether for the biological material to obtain a liquefied dimethyl ether solution including the component; separating the solution from the biological material; and volatilizing or separating the liquefied dimethyl ether from the solution.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: January 10, 2023
    Assignee: Ricoh Company, Ltd.
    Inventors: Shogo Torii, Satoshi Shinohara, Shogo Suzuki
  • Publication number: 20210313473
    Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.
    Type: Application
    Filed: May 5, 2021
    Publication date: October 7, 2021
    Inventors: Shunpei YAMAZAKI, Satoshi SHINOHARA
  • Patent number: 11011652
    Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: May 18, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Shinohara
  • Publication number: 20210001247
    Abstract: A method of producing an extract of an animal-derived or plant-derived biological material includes: extracting a component in the biological material using liquefied dimethyl ether for the biological material to obtain a liquefied dimethyl ether solution including the component; separating the solution from the biological material; and volatilizing or separating the liquefied dimethyl ether from the solution.
    Type: Application
    Filed: March 12, 2019
    Publication date: January 7, 2021
    Inventors: Shogo TORII, Satoshi SHINOHARA, Shogo SUZUKI
  • Publication number: 20200261859
    Abstract: A manufacturing method for a separation membrane element is a manufacturing method for a spiral-wound type separation membrane element including a perforated hollow tube and a laminated body that includes a separation membrane and is wound around the hollow tube. The manufacturing method includes pressing a press member against a portion of the laminated body that is wound around the hollow tube. The pressing presses the press member to satisfy respective relations defined by formulas (1) and (2): 0.1×Ps1?Pe??(1), and 0.1×Ps2?Pe??(2).
    Type: Application
    Filed: February 11, 2020
    Publication date: August 20, 2020
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Satoshi SHINOHARA, Hisaaki MIYAMOTO
  • Publication number: 20200243689
    Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.
    Type: Application
    Filed: April 14, 2020
    Publication date: July 30, 2020
    Inventors: Shunpei YAMAZAKI, Satoshi SHINOHARA
  • Publication number: 20200179568
    Abstract: A method for producing a decellularized tissue includes steps of lysing a cell of a biological tissue using a liquid containing a liquefied gas, and degrading a nucleic acid component contained in the lysed cell of the biological tissue using a nucleolytic enzyme.
    Type: Application
    Filed: March 29, 2018
    Publication date: June 11, 2020
    Inventors: Satoshi SHINOHARA, Shogo SUZUKI, Shogo TORII
  • Patent number: 10658522
    Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: May 19, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Shinohara
  • Publication number: 20200002669
    Abstract: A decellularized tissue producing method includes degrading DNA included in a biological tissue in which cells are destroyed, by using a first treatment liquid; degreasing the biological tissue in which the DNA is degraded, by using a second treatment liquid; and washing the degreased biological tissue, by using a third treatment liquid. At least one of the degrading, the degreasing, and the washing is performed by a circulation method.
    Type: Application
    Filed: June 24, 2019
    Publication date: January 2, 2020
    Applicant: Ricoh Company, Ltd.
    Inventors: Satoshi SHINOHARA, Shogo SUZUKI
  • Patent number: 10363552
    Abstract: Provided is a honeycomb fired body in which the pressure loss in the initial state where PM has not accumulated is sufficiently low, the strength is sufficiently high, and the heat capacity is not small.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: July 30, 2019
    Assignee: IBIDEN CO., LTD.
    Inventors: Shunpei Enoshita, Satoshi Shinohara
  • Patent number: 10239915
    Abstract: This invention is intended to produce a novel functional material through solubilization and molecular weight reduction of a water-insoluble polymeric compound, such as a water-insoluble protein or water-insoluble polysaccharide, in a simple and efficient manner.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: March 26, 2019
    Assignees: JELLYFISH RESEARCH LABORATORIES, INC., MARUWA OIL & FAT CO., LTD.
    Inventors: Satoshi Shinohara, Takayuki Baba, Koji Kihira
  • Publication number: 20180366588
    Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.
    Type: Application
    Filed: August 2, 2018
    Publication date: December 20, 2018
    Inventors: Shunpei YAMAZAKI, Satoshi SHINOHARA
  • Patent number: 10074748
    Abstract: A semiconductor device in which deterioration of electrical characteristics which becomes more noticeable as the transistor is miniaturized can be suppressed is provided. The semiconductor device includes an oxide semiconductor stack in which a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer are stacked in this order from the substrate side over a substrate; a source electrode layer and a drain electrode layer which are in contact with the oxide semiconductor stack; a gate insulating film over the oxide semiconductor stack, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating film. The first oxide semiconductor layer includes a first region. The gate insulating film includes a second region. When the thickness of the first region is TS1 and the thickness of the second region is TG1, TS1?TG1.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: September 11, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daisuke Matsubayashi, Satoshi Shinohara, Wataru Sekine
  • Patent number: 10043918
    Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: August 7, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Shinohara
  • Patent number: 9905702
    Abstract: Provided is a bottom-gate transistor including an oxide semiconductor, in which electric-field concentration which might occur in the vicinity of an end portion of a drain electrode layer (and the vicinity of an end portion of a source electrode layer) when a high gate voltage is applied to a gate electrode layer is reduced and degradation of switching characteristics is suppressed, so that the reliability is improved. The cross-sectional shape of an insulating layer which overlaps over a channel formation region is a tapered shape. The thickness of the insulating layer which overlaps over the channel formation region is 0.3 ?m or less, preferably 5 nm or more and 0.1 ?m or less. The taper angle ? of a lower end portion of the cross-sectional shape of the insulating layer which overlaps over the channel formation region is 60° or smaller, preferably 45° or smaller, further preferably 30° or smaller.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: February 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiko Hayakawa, Satoshi Shinohara
  • Publication number: 20170309753
    Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.
    Type: Application
    Filed: July 10, 2017
    Publication date: October 26, 2017
    Inventors: Shunpei YAMAZAKI, Satoshi SHINOHARA