Patents by Inventor Satoshi Shiraki

Satoshi Shiraki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200043834
    Abstract: A semiconductor device includes a metal chip mounting member and a semiconductor chip bonded to the chip mounting member through a metal sintered material, wherein the metal sintered material includes a first portion overlapping the semiconductor chip in a plan view, and includes a second portion surrounding the semiconductor chip in the plan view, and wherein a porosity ratio of the first portion is greater than or equal to 1% and less than 15%, and a porosity ratio of the second portion is greater than or equal to 15% and less than or equal to 50%.
    Type: Application
    Filed: July 12, 2019
    Publication date: February 6, 2020
    Inventor: Satoshi SHIRAKI
  • Patent number: 10366826
    Abstract: A dual-mode choke coil includes: a lower core that has a first through fourth columnar body; a first upper core and a second upper core; a first coil in which two coil conductors are respectively wound onto the first columnar body and a third columnar body in mutually different directions and are connected in series; and a second coil in which two coil conductors are respectively wound onto a second columnar body and the fourth columnar body in mutually different directions and are connected in series, and in which the winding direction of the coil conductor of the second columnar body is the same as that of the coil conductor of the first columnar body. With this configuration, both common mode noise and normal mode noise can be reduced.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: July 30, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasuhiro Shiraki, Satoshi Yoneda, Katsuhiko Omae, Nobuyuki Haruna
  • Patent number: 9941232
    Abstract: An electronic component device includes: a lower wiring substrate; an electronic component on the lower wiring substrate; an upper wiring substrate disposed above the lower wiring substrate and the electronic component; a bump conductor disposed between the lower wiring substrate and the upper wiring substrate to electrically connect the lower wiring substrate and the upper wiring substrate; and a sealing resin provided between the lower wiring substrate and the upper wiring substrate to seal the electronic component and the bump conductor. The upper wiring substrate includes: a first wiring layer directly connected to the bump conductor; and a first insulating layer having an opening portion through which the first wiring layer is exposed and disposed to cover the first wiring layer. The first wiring layer and the first insulating layer are not opposed to the electronic component in a thickness direction of the electronic component device.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: April 10, 2018
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Satoshi Shiraki, Koichi Tanaka, Masahiro Kyozuka, Tomohiro Suzuki
  • Patent number: 9935053
    Abstract: An electronic component integrated substrate includes a first substrate including a first pad, a first solder resist layer provided with a first open portion that selectively exposes the first pad, and a connection pad formed on the first solder resist layer, and electrically connected to the first pad; a second substrate, stacked on the first substrate, including a second pad, and a second solder resist layer formed on the second pad and provided with a second open portion that selectively exposes the second pad; an electronic component mounted on the first substrate and sandwiched between the first substrate and the second substrate; and a substrate connection member that electrically connects the connection pad and the second pad with each other, the diameter of the connection pad being larger than each of the diameter of the first pad and the diameter of the second open portion.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: April 3, 2018
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Satoshi Shiraki, Koichi Tanaka
  • Publication number: 20170221829
    Abstract: An electronic component integrated substrate includes a first substrate including a first pad, a first solder resist layer provided with a first open portion that selectively exposes the first pad, and a connection pad formed on the first solder resist layer, and electrically connected to the first pad; a second substrate, stacked on the first substrate, including a second pad, and a second solder resist layer formed on the second pad and provided with a second open portion that selectively exposes the second pad; an electronic component mounted on the first substrate and sandwiched between the first substrate and the second substrate; and a substrate connection member that electrically connects the connection pad and the second pad with each other, the diameter of the connection pad being larger than each of the diameter of the first pad and the diameter of the second open portion.
    Type: Application
    Filed: January 19, 2017
    Publication date: August 3, 2017
    Inventors: Satoshi SHIRAKI, Koichi TANAKA
  • Publication number: 20170062370
    Abstract: An electronic component device includes: a lower wiring substrate; an electronic component on the lower wiring substrate; an upper wiring substrate disposed above the lower wiring substrate and the electronic component; a bump conductor disposed between the lower wiring substrate and the upper wiring substrate to electrically connect the lower wiring substrate and the upper wiring substrate; and a sealing resin provided between the lower wiring substrate and the upper wiring substrate to seal the electronic component and the bump conductor. The upper wiring substrate includes: a first wiring layer directly connected to the bump conductor; and a first insulating layer having an opening portion through which the first wiring layer is exposed and disposed to cover the first wiring layer. The first wiring layer and the first insulating layer are not opposed to the electronic component in a thickness direction of the electronic component device.
    Type: Application
    Filed: August 25, 2016
    Publication date: March 2, 2017
    Inventors: Satoshi Shiraki, Koichi Tanaka, Masahiro Kyozuka, Tomohiro Suzuki
  • Patent number: 9524931
    Abstract: A wiring substrate includes a block with substrates laid out in an array. The block includes corners and a plan view center. Each substrate includes a substrate body. Pads are formed on the substrate body. Each pad includes a pad surface. The pads of the substrates include first pads, which are the pads of one of the substrates located in at least one of the corners of the block. The pad surface of each of the first pads includes a first axis extending from the first pad toward the plan view center of the block. The pad surface of each of the first pads has a first length along the corresponding first axis and a second length along a second axis, which is orthogonal to the first axis. The first length is longer than the second length.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: December 20, 2016
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Satoshi Shiraki
  • Patent number: 9240445
    Abstract: A lateral semiconductor device includes a semiconductor layer, an insulating layer, and a resistive field plate. The semiconductor layer includes a first semiconductor region and a second semiconductor region at a surface portion, and the second semiconductor region makes a circuit around the first semiconductor region. The insulating layer is formed on a surface of the semiconductor layer and is disposed between the first and second semiconductor regions. The resistive field plate is formed on a surface of the insulating layer. Between the first and second semiconductor regions, a first section and a second section are adjacent to each other along a circumferential direction around the first semiconductor region. The resistive field plate includes first and second resistive field plate sections respectively formed in the first and second sections, and the first and second resistive field plate sections are separated from each other.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: January 19, 2016
    Assignee: DENSO CORPORATION
    Inventors: Takashi Suzuki, Norihito Tokura, Satoshi Shiraki, Shigeki Takahashi, Youichi Ashida, Akira Yamada
  • Patent number: 9214536
    Abstract: A lateral insulated gate bipolar transistor includes a semiconductor substrate including a drift layer, a collector region, a channel layer, an emitter region, a gate insulating layer, a gate electrode, a collector electrode, an emitter electrode, and a barrier layer. The barrier layer is disposed along either side of the collector region and is located to a depth deeper than a bottom of the channel layer. The barrier layer has an impurity concentration that is higher than an impurity concentration of the drift layer. The barrier layer has a first end close to the collector region and a second end far from the collector region. The first end is located between the channel layer and the collector region, and the second end is located on the bottom of the channel layer.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: December 15, 2015
    Assignee: DENSO CORPORATION
    Inventors: Shigeki Takahashi, Norihito Tokura, Satoshi Shiraki, Youichi Ashida, Akio Nakagawa
  • Patent number: 9136362
    Abstract: A semiconductor device with a lateral element includes a semiconductor substrate, first and second electrodes on the substrate, and a resistive field plate extending from the first electrode to the second electrode. The lateral element passes a current between the first and second electrodes. A voltage applied to the second electrode is less than a voltage applied to the first electrode. The resistive field plate has a first end portion and a second end portion opposite to the first end portion. The second end portion is located closer to the second electrode than the first end portion. An impurity concentration in the second end portion is equal to or greater than 1×1018 cm?3.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 15, 2015
    Assignee: DENSO CORPORATION
    Inventors: Takeshi Sakai, Akira Yamada, Shigeki Takahashi, Youichi Ashida, Satoshi Shiraki
  • Publication number: 20150228571
    Abstract: A wiring substrate includes a block with substrates laid out in an array. The block includes corners and a plan view center. Each substrate includes a substrate body. Pads are formed on the substrate body. Each pad includes a pad surface. The pads of the substrates include first pads, which are the pads of one of the substrates located in at least one of the corners of the block. The pad surface of each of the first pads includes a first axis extending from the first pad toward the plan view center of the block. The pad surface of each of the first pads has a first length along the corresponding first axis and a second length along a second axis, which is orthogonal to the first axis. The first length is longer than the second length.
    Type: Application
    Filed: January 8, 2015
    Publication date: August 13, 2015
    Inventor: Satoshi SHIRAKI
  • Patent number: 9036362
    Abstract: An electronic component incorporated substrate includes a first substrate and a second substrate that are electrically connected to each other by a spacer unit. An electronic component is mounted on the first substrate and arranged between the first substrate and the second substrate. An encapsulating resin fills a space between the first substrate and the second substrate to encapsulate the electronic component. The spacer unit includes a stacked structure of a metal post and a solder ball stacked in a stacking direction of the first substrate and the second substrate. The spacer unit further includes an insulation layer that is formed on the second substrate and covers a side wall of the metal post.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: May 19, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Koichi Tanaka, Nobuyuki Kurashima, Hajime Iizuka, Satoshi Shiraki
  • Publication number: 20150115612
    Abstract: The invention relates to a rotor for a dynamo-electric machine having: a rotor body which rotates about a rotation axis which runs in the direction of gravity, winding elements which are arranged in slots which run axially in the rotor body, two winding heads which are arranged above and below the rotor body in the axial direction, wherein the winding elements emerge from the slots in the axial direction in the region of the winding heads and are connected to further winding elements, a winding head carrier for each of the winding heads, which winding head carrier is arranged radially within the winding head and coaxially to the rotation axis, and which winding head carrier is fixed at least indirectly on the rotor body, or on a component which revolves with said rotor body, in a rotationally fixed manner and such that it can move in the direction of the rotation axis.
    Type: Application
    Filed: June 14, 2012
    Publication date: April 30, 2015
    Inventors: Phillipp Eilebrecht, Satoshi Shiraki, Holger Henning
  • Patent number: 8987919
    Abstract: A built-in electronic component substrate includes a first substrate, an electronic component including side surfaces and mounted on the first substrate, a first resin provided on the first substrate and covering the side surfaces of the electronic component, a second substrate provided above the electronic component and the first resin and layered on the first substrate, a substrate connection member provided between the first and the second substrates and electrically connecting the first and the second substrates, a second resin filling in between the electronic component and the second substrate and in between the first resin and the second substrate, and a third resin filling in between the first and the second substrates and encapsulating the substrate connection member, the electronic component, the first resin, and the second resin.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: March 24, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Koichi Tanaka, Nobuyuki Kurashima, Hajime Iizuka, Satoshi Shiraki
  • Patent number: 8854033
    Abstract: A semiconductor device having a lateral semiconductor element includes a semiconductor substrate, a first electrode on the substrate, a second electrode on the substrate, and an isolation structure located in the substrate to divide the substrate into a first island and a second island electrically insulated from the first island. The lateral semiconductor element includes a main cell located in the first island and a sense cell located in the second island. The main cell causes a first current to flow between the first electrode and the second electrode so that the first current flows in a lateral direction along the surface of the substrate. The first current is detected by detecting a second current flowing though the sense cell.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: October 7, 2014
    Assignee: DENSO CORPORATION
    Inventors: Satoshi Shiraki, Norihito Tokura, Shigeki Takahashi, Masahiro Yamamoto, Akira Yamada, Hiroyasu Kudo, Youichi Ashida, Akio Nakagawa
  • Publication number: 20140210109
    Abstract: A built-in electronic component substrate includes a first substrate, an electronic component including side surfaces and mounted on the first substrate, a first resin provided on the first substrate and covering the side surfaces of the electronic component, a second substrate provided above the electronic component and the first resin and layered on the first substrate, a substrate connection member provided between the first and the second substrates and electrically connecting the first and the second substrates, a second resin filling in between the electronic component and the second substrate and in between the first resin and the second substrate, and a third resin filling in between the first and the second substrates and encapsulating the substrate connection member, the electronic component, the first resin, and the second resin.
    Type: Application
    Filed: January 9, 2014
    Publication date: July 31, 2014
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Koichi TANAKA, Nobuyuki KURASHIMA, Hajime IIZUKA, Satoshi SHIRAKI
  • Patent number: 8791690
    Abstract: A semiconductor device having a lateral semiconductor element includes a semiconductor substrate, a first electrode on the substrate, a second electrode on the substrate, and an isolation structure located in the substrate to divide the substrate into a first island and a second island electrically insulated from the first island. The lateral semiconductor element includes a main cell located in the first island and a sense cell located in the second island. The main cell causes a first current to flow between the first electrode and the second electrode so that the first current flows in a lateral direction along the surface of the substrate. The first current is detected by detecting a second current flowing though the sense cell.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: July 29, 2014
    Assignee: DENSO CORPORATION
    Inventors: Satoshi Shiraki, Norihito Tokura, Shigeki Takahashi, Masahiro Yamamoto, Akira Yamada, Hiroyasu Kudo, Youichi Ashida, Akio Nakagawa
  • Publication number: 20140070271
    Abstract: A lateral insulated gate bipolar transistor includes a semiconductor substrate including a drift layer, a collector region, a channel layer, an emitter region, a gate insulating layer, a gate electrode, a collector electrode, an emitter electrode, and a barrier layer. The barrier layer is disposed along either side of the collector region and is located to a depth deeper than a bottom of the channel layer. The barrier layer has an impurity concentration that is higher than an impurity concentration of the drift layer. The barrier layer has a first end close to the collector region and a second end far from the collector region. The first end is located between the channel layer and the collector region, and the second end is located on the bottom of the channel layer.
    Type: Application
    Filed: November 12, 2013
    Publication date: March 13, 2014
    Applicant: DENSO CORPORATION
    Inventors: Shigeki TAKAHASHI, Norihito TOKURA, Satoshi SHIRAKI, Youichi ASHIDA, Akio NAKAGAWA
  • Publication number: 20140063764
    Abstract: An electronic component incorporated substrate includes a first substrate and a second substrate that are electrically connected to each other by a spacer unit. An electronic component is mounted on the first substrate and arranged between the first substrate and the second substrate. An encapsulating resin fills a space between the first substrate and the second substrate to encapsulate the electronic component. The spacer unit includes a stacked structure of a metal post and a solder ball stacked in a stacking direction of the first substrate and the second substrate. The spacer unit further includes an insulation layer that is formed on the second substrate and covers a side wall of the metal post.
    Type: Application
    Filed: August 19, 2013
    Publication date: March 6, 2014
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Koichi TANAKA, Nobuyuki KURASHIMA, Hajime IIZUKA, Satoshi SHIRAKI
  • Publication number: 20140048911
    Abstract: A lateral semiconductor device includes a semiconductor layer, an insulating layer, and a resistive field plate. The semiconductor layer includes a first semiconductor region and a second semiconductor region at a surface portion, and the second semiconductor region makes a circuit around the first semiconductor region. The insulating layer is formed on a surface of the semiconductor layer and is disposed between the first and second semiconductor regions. The resistive field plate is formed on a surface of the insulating layer. Between the first and second semiconductor regions, a first section and a second section are adjacent to each other along a circumferential direction around the first semiconductor region. The resistive field plate includes first and second resistive field plate sections respectively formed in the first and second sections, and the first and second resistive field plate sections are separated from each other.
    Type: Application
    Filed: May 10, 2012
    Publication date: February 20, 2014
    Applicant: DENSO CORPORATION
    Inventors: Takashi Suzuki, Norihito Tokura, Satoshi Shiraki, Shigeki Takahashi, Youichi Ashida, Akira Yamada