Patents by Inventor Satoshi Tamura

Satoshi Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10529843
    Abstract: A semiconductor device includes: a substrate; a drift layer which is disposed on the substrate and has a groove; an underlayer which is disposed above the drift layer; a first opening which penetrates the underlayer to reach the drift layer; an electron transit layer and an electron supply layer which are disposed to cover the first opening; a second opening which penetrates the electron supply layer and the electron transit layer to reach the underlayer; a gate electrode which is disposed above the electron supply layer at a position corresponding to a position of the first opening; a source electrode which is disposed to cover the second opening and in contact with the underlayer; and a drain electrode which is disposed on a backside surface of the substrate. A bottom surface of the groove is closer to the substrate than a bottom surface of the first opening.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: January 7, 2020
    Assignee: Panasonic Corporation
    Inventors: Daisuke Shibata, Satoshi Tamura, Masahiro Ishida
  • Patent number: 10510656
    Abstract: A semiconductor device includes: a high-side transistor having a first gate electrode, first drain electrodes and first source electrodes; a low-side transistor having a second gate electrode, second drain electrodes and second source electrodes; a plurality of first drain pads that are disposed above the first drain electrodes and are electrically connected to the first drain electrodes; a plurality of first source pads that are disposed above the second source electrodes and are electrically connected to the second source electrodes; a plurality of first common interconnects that are disposed above the first source electrodes and above the second drain electrodes and are electrically connected to the first source electrodes and the second drain electrodes; and a plurality of second common interconnects that are connected to the first common interconnects, and extend in a direction that intersects with the first common interconnects.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: December 17, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yusuke Kinoshita, Satoshi Tamura
  • Publication number: 20190326465
    Abstract: A semiconductor relay includes: a light-emitting element; and a light-receiving element facing the light-emitting element. The light-receiving element includes: a substrate; a semiconductor layer having a direct transition type, the semiconductor layer being disposed on the substrate and having a semi-insulating property; a first electrode having at least a part in contact with the semiconductor layer; and a second electrode having at least a part in contact with either one of the semiconductor layer and the substrate, in a position separated from the first electrode. The semiconductor layer is reduced in resistance by absorbing light from the light-emitting element.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 24, 2019
    Applicant: PANASONIC CORPORATION
    Inventors: Daisuke Shibata, Satoshi Tamura, Shinji Ujita, Nanako Hirashita, Masahiro Ogawa, Ryo Kajitani
  • Patent number: 10367401
    Abstract: In a 4-pole, 6-slot, 18-segment electric motor, one forward winding coil (91) and two reverse winding coils (92, 93) are wound on each tooth (12). When the forward winding coils are formed of coils corresponding to a U phase, a V phase, and a W phase and the reverse winding coils are formed of coils corresponding to a “?U” phase, a “?V” phase, and a “?W” phase, the coils, which correspond to a U phase, a “?W” phase, a “?W” phase, a V phase, a “?U” phase, a “?U” phase, a W phase, a “?V” phase, and a “?V” phase, are electrically connected in this order between the adjacent segments.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: July 30, 2019
    Assignee: Mitsuba Corporation
    Inventors: Natsumi Tamura, Hiroto Tanaka, Teppei Tokizaki, Satoshi Tamura
  • Patent number: 10355143
    Abstract: A nitride semiconductor device includes: a substrate having a first major surface and a second major surface; a first nitride semiconductor layer of an n-type which is disposed on the first major surface and has a protrusion; a second nitride semiconductor layer of a p-type disposed on the protrusion; a first anode electrode disposed above the first nitride semiconductor layer and the second nitride semiconductor layer; and a cathode electrode disposed under the second major surface, and a lateral surface of the protrusion is inclined by a first angle with respect to the first major surface.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: July 16, 2019
    Assignee: PANASONIC CORPORATION
    Inventors: Ryo Kajitani, Daisuke Shibata, Kenichiro Tanaka, Satoshi Tamura, Masahiro Ishida, Tetsuzo Ueda
  • Publication number: 20190185295
    Abstract: According to one embodiment, a user detection system includes a camera, a boundary detector, a user detector and a controller. The camera is installed in a peripheral region of a door, and captures a running region when opening or closing the door and a region near the door. The boundary detector detects a boundary between a first structure and a second structure in the region near the door based on an image captured by the camera. The user detector detects whether there is a user in the running region based on a result detected by the boundary detector. The controller controls an open/close operation of the door based on a result detected by the user detector.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 20, 2019
    Applicant: TOSHIBA ELEVATOR KABUSHIKI KAISHA
    Inventors: Shuhei NODA, Kentaro YOKOI, Satoshi TAMURA, Sayumi KIMURA
  • Publication number: 20190172209
    Abstract: According to one embodiment, an image detection system includes an imaging apparatus, an edge extraction unit, a specific-edge extraction unit, a candidate area extraction unit, and a to-be-detected area determination unit. The edge extraction unit extracts edges each representing a boundary line between areas with different features. The specific-edge extraction unit extracts specific edges including at least remaining edges present in background image and input image. The candidate area extraction unit extracts candidate areas for a preset area to be detected. The to-be-detected area determination unit determines the area to be detected from candidate areas extracted.
    Type: Application
    Filed: July 23, 2018
    Publication date: June 6, 2019
    Applicant: TOSHIBA ELEVATOR KABUSHIKI KAISHA
    Inventors: Kentaro YOKOI, Shuhei NODA, Satoshi TAMURA, Sayumi KIMURA
  • Patent number: 10270321
    Abstract: An electric motor includes: brushes (31) that are brought into sliding contact with a commutator of an armature that is fixed to a rotation shaft and feeds electric power; a brush holder stay (33) that supports the brushes (31) via brush holders (41); noise prevention elements (110) that are electrically connected to the brushes (31); and terminals (130) and jump wires (141) that electrically connect between the brush holders (41) and the noise prevention elements (110), wherein first connection portions, which connect between the noise prevention elements (110) and the terminals (130), and second connection portions, which connect between the terminals (130) and the jump wires (141), are both disposed only on a first surface (S1) of the brush holder stay (33).
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: April 23, 2019
    Assignee: Mitsuba Corporation
    Inventors: Natsumi Tamura, Tomoo Iijima, Teppei Tokizaki, Satoshi Tamura
  • Patent number: 10256041
    Abstract: A polypropylene (F) for film condensers having the following requirements: (1) an MFR (JIS K 7210, 230° C., 2.16 kg load) in the range of 1-10 (g/10 min), (2) an mmmm fraction that is at least 93%, (3) a <2,1>erythro position defect amount as measured using 13C-NMR that is less than 0.1 mol %, (4) ash content obtained by complete combustion in atmosphere that is at most 50 ppm, (5) chlorine content as measured by ion chromatography that is at most 5 ppm; and (6) is obtained by including a propylene homopolymer for which Mw/Mn as measured via GPC is 6.5-12 and an ?-crystal nucleating agent with a melting point of at most 290° C.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: April 9, 2019
    Assignee: PRIME POLYMER CO., LTD.
    Inventors: Satoshi Tamura, Jun Birukawa, Hiroki Shimizu
  • Publication number: 20190101331
    Abstract: A circulation channel circularly supplying air heated by a burner is connected to a drying chamber into which a painted workpiece is supplied. The circulation channel includes a flame holding cylinder surrounding a flame of the burner and a casing surrounding the flame holding cylinder from outside and protrudes further than the flame holding cylinder toward a front end side, opposite to a side of the burner, of the flame holding cylinder. The casing includes a low temperature air inlet port that introduces low temperature air from outside into the casing, an exhaust port that exhausts high temperature air heated by the burner and the low temperature air to the circulation channel, and a mixing mechanism that is formed in the casing and mixes the high temperature air and the low temperature air before the high temperature air and the low temperature air are exhausted from the exhaust port.
    Type: Application
    Filed: November 15, 2016
    Publication date: April 4, 2019
    Applicant: TRINITY INDUSTRIAL CORPORATION
    Inventor: Satoshi TAMURA
  • Patent number: 10164011
    Abstract: A nitride semiconductor device includes a substrate; a nitride semiconductor layered structure disposed on the substrate and having a channel region; a first electrode and a second electrode both disposed on the nitride semiconductor layered structure; a first p-type nitride semiconductor layer disposed between the first electrode and the second electrode; and a first gate electrode disposed on the first p-type nitride semiconductor layer. The nitride semiconductor layered structure includes a first recess. The first p-type nitride semiconductor layer is at least partially disposed inside the first recess, and is separated from a side surface of the first recess.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: December 25, 2018
    Assignee: PANASONIC CORPORATION
    Inventors: Yusuke Kinoshita, Hidekazu Umeda, Satoshi Tamura
  • Publication number: 20180350917
    Abstract: A semiconductor device includes: a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer; a first opening penetrating the second nitride semiconductor layer; an electron transit layer and an electron supply layer which are formed along an upper surface of the second nitride semiconductor layer and a recessed surface of the first opening; a gate electrode disposed above the electron supply layer; a second opening penetrating the electron supply layer and the electron transit layer; a source electrode disposed to cover the second opening and electrically connected to the second nitride semiconductor layer; and a drain electrode disposed on a back surface of the substrate. The electron supply layer has a side surface formed along a side surface of the first opening. The gate electrode is not disposed on the side surface of the electron supply layer.
    Type: Application
    Filed: August 6, 2018
    Publication date: December 6, 2018
    Inventors: Shinji UJITA, Daisuke SHIBATA, Satoshi TAMURA
  • Publication number: 20180350965
    Abstract: A semiconductor device includes: a substrate; a drift layer which is disposed on the substrate and has a groove; an underlayer which is disposed above the drift layer; a first opening which penetrates the underlayer to reach the drift layer; an electron transit layer and an electron supply layer which are disposed to cover the first opening; a second opening which penetrates the electron supply layer and the electron transit layer to reach the underlayer; a gate electrode which is disposed above the electron supply layer at a position corresponding to a position of the first opening; a source electrode which is disposed to cover the second opening and in contact with the underlayer; and a drain electrode which is disposed on a backside surface of the substrate. A bottom surface of the groove is closer to the substrate than a bottom surface of the first opening.
    Type: Application
    Filed: August 7, 2018
    Publication date: December 6, 2018
    Inventors: Daisuke SHIBATA, Satoshi TAMURA, Masahiro ISHIDA
  • Publication number: 20180286588
    Abstract: A polypropylene (F) for film condensers having the following requirements: (1) an MFR (JIS K 7210, 230° C., 2.16 kg load) in the range of 1-10 (g/10 min), (2) an mmmm fraction that is at least 93%, (3) a <2,1>erythro position defect amount as measured using 13C-NMR that is less than 0.1 mol %, (4) ash content obtained by complete combustion in atmosphere that is at most 50 ppm, (5) chlorine content as measured by ion chromatography that is at most 5 ppm; and (6) is obtained by including a propylene homopolymer for which Mw/Mn as measured via GPC is 6.5-12 and an ?-crystal nucleating agent with a melting point of at most 290° C.
    Type: Application
    Filed: March 30, 2016
    Publication date: October 4, 2018
    Applicant: PRIME POLYMER CO., LTD.
    Inventors: Satoshi TAMURA, Jun BIRUKAWA, Hiroki SHIMIZU
  • Patent number: 10011693
    Abstract: [Problem] To provide polypropylene for a microporous film having excellent heat resistance and strength. [Solution] Polypropylene for a microporous film satisfying the following requirements (1) and (2): (1) the weight-average molecular weight (Mw) value, as determined by gel permeation chromatography (GPC), is not less than 100,000 but less than 800,000, the value (Mw/Mn) obtained by dividing the weight-average molecular weight by the number-average molecular weight is more than 7.0 but not more than 12.0, and the value (Mz/Mw) obtained by dividing the Z-average molecular weight by the weight-average molecular weight is not less than 3.8 but not more than 9.0, and (2) the mesopentad fraction, as measured by 13C-NMR (nuclear magnetic resonance method), is not less than 95.5%.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: July 3, 2018
    Assignee: PRIME POLYMER CO., LTD.
    Inventors: Yoshio Yanagishita, Chikara Satou, Satoshi Tamura, Katsutoshi Ohta
  • Publication number: 20180145166
    Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 ?m-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.
    Type: Application
    Filed: January 17, 2018
    Publication date: May 24, 2018
    Inventors: Hidekazu UMEDA, Kazuhiro KAIBARA, Satoshi TAMURA
  • Publication number: 20180097123
    Abstract: A nitride semiconductor device includes: a substrate having a first major surface and a second major surface; a first nitride semiconductor layer of an n-type which is disposed on the first major surface and has a protrusion; a second nitride semiconductor layer of a p-type disposed on the protrusion; a first anode electrode disposed above the first nitride semiconductor layer and the second nitride semiconductor layer; and a cathode electrode disposed under the second major surface, and a lateral surface of the protrusion is inclined by a first angle with respect to the first major surface.
    Type: Application
    Filed: November 17, 2017
    Publication date: April 5, 2018
    Inventors: Ryo Kajitani, Daisuke Shibata, Kenichiro Tanaka, Satoshi Tamura, Masahiro Ishida, Tetsuzo Ueda
  • Publication number: 20180083507
    Abstract: A motor with a speed reducer includes a motor (4) received in a motor housing (2), a speed reducer (5) received in the motor housing (2) and that is driven by receiving power from a motor shaft of the motor (4) and that reduces rotation of a rotor boss (43) and outputs the reduced rotation, and a drive shaft (7) received in the motor housing (2), connected to an output shaft (58) of the speed reducer (5) via a transmission belt (6) and that drives a driven body, wherein the rotor boss (43) and the output shaft (58) are disposed coaxially, and the output shaft (58) and the drive shaft (7) are disposed parallel in a radial direction.
    Type: Application
    Filed: April 12, 2016
    Publication date: March 22, 2018
    Inventors: Teppei Tokizaki, Satoshi Tamura, Natsumi Tamura, Hiroto Tanaka
  • Publication number: 20180072828
    Abstract: Provided is a polypropylene resin composition which is good in extrusion property, which is good in appearance and low in variation in thickness when formed into a film, which is well-balanced in dynamic characteristics, and which has high heat resistance. A polypropylene resin composition satisfying the following requirements (1) to (3): (1) a melt flow rate (MFR) measured under a load of 2.16 kg at 230° C. according to ASTM D1238 is 1 to 10 g/10 min; (2) a pentad isotactic fraction measured using 13C-NMR is 0.930 or more; and (3) Mz is 600000 to 1400000, and Mw/Mn is 6.5 to 14.0.
    Type: Application
    Filed: March 30, 2016
    Publication date: March 15, 2018
    Applicant: PRIME POLYMER CO., LTD.
    Inventors: Satoshi TAMURA, Masashi HIGUCHI
  • Patent number: 9911843
    Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 ?m-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: March 6, 2018
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hidekazu Umeda, Kazuhiro Kaibara, Satoshi Tamura