Patents by Inventor Satoshi Tanaka

Satoshi Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11657651
    Abstract: An information processing apparatus monitors a plurality of persons on a premises by one or more image sensors installed on the premises. The information processing apparatus includes a controller configured to determine a tendency of behavior of at least one person of the plurality of persons according to a length of a blank time, the blank time being a time during which the at least one person does not appear in an image captured by the one or more image sensors.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: May 23, 2023
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takayuki Oidemizu, Kazuyuki Inoue, Ryosuke Kobayashi, Yurika Tanaka, Tomokazu Maya, Satoshi Komamine
  • Patent number: 11658622
    Abstract: A power amplifier circuit includes a lower transistor having a first terminal, a second terminal connected to ground, and a third terminal, wherein a first power supply voltage is supplied to the first terminal, and an input signal is supplied to the third terminal; a first capacitor; an upper transistor having a first terminal, a second terminal connected to the first terminal of the lower transistor via the first capacitor, and a third terminal, wherein a second power supply voltage is supplied to the first terminal, an amplified signal is outputted to an output terminal from the first terminal, and a driving voltage is supplied to the third terminal; a first inductor that connects the second terminal of the upper transistor to ground; a voltage regulator circuit; and at least one termination circuit that short-circuits an even-order harmonic or odd-order harmonic of the amplified signal to ground potential.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: May 23, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Kazuo Watanabe, Yusuke Tanaka, Satoshi Arayashiki
  • Patent number: 11659126
    Abstract: An image processing apparatus includes a display device and a processor. The processor is configured to generate a first screen for display on the display device and on which one of a plurality of malfunctioning part candidates of the image processing apparatus and one of a plurality of timings at which a particular sound was output by the image processing apparatus that malfunctioned, are selectable, when a first malfunctioning part candidate and a first timing are selected on the first screen, generate a second screen for display on the display device and on which one or more reference sounds corresponding to the particular sound are selectable, and when one of the reference sounds is selected on the second screen, generate error information indicating the first malfunctioning part candidate and the selected reference sound.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: May 23, 2023
    Assignee: Toshiba Tec Kabushiki Kaisha
    Inventors: Sou Miyazaki, Hiroyo Tanaka, Kazuhiro Ogura, Masaki Narahashi, Satoshi Oyama, Tatsuya Inagi
  • Patent number: 11646704
    Abstract: A power amplifier circuit includes a first transistor that amplifies a first signal and outputs a second signal; a second transistor that amplifies the second signal and outputs a third signal; a bias circuit that supplies a bias current to a base of the second transistor; and a bias adjustment circuit that adjusts the bias current by subjecting the first signal to detection. The bias adjustment circuit controls the bias current such that a first current extracted from the bias circuit depends on a magnitude of the first signal.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: May 9, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takayuki Tsutsui, Masao Kondo, Satoshi Tanaka
  • Publication number: 20230134478
    Abstract: Provided is a cell culture vessel for culturing cells with a high density having excellent gas permeability and strength. A bag-shaped cell culture vessel of a closed system includes at least one port and mutually opposed planar substrates. At least one of the planar substrates is formed of a gas permeable film, the at least one gas permeable film has an outer surface provided with a protruding portion having a shape different from an inner surface shape of the gas permeable film, a culture space for culturing cells is provided in the inner surface side of the gas permeable film, and when the gas permeable film is brought in contact with a planar surface, a space enabling ventilation is formed between the gas permeable film and the planar surface by the protruding portion.
    Type: Application
    Filed: December 29, 2022
    Publication date: May 4, 2023
    Inventors: Osamu KOSEKI, Satoshi TANAKA, Takahiko TOTANI, Yosuke MATSUOKA, Takaharu NISHIYAMA
  • Publication number: 20230132964
    Abstract: A power amplifier circuit includes a first transistor having an emitter electrically connected to a common potential, a base to which a first high-frequency signal is input, and a collector from which a third high-frequency signal is output; a second transistor having an emitter electrically connected to the common potential, a base to which a second high-frequency signal is input, and a collector from which a fourth high-frequency signal is output; a first capacitance circuit electrically connected between the collector of the second transistor and the base of the first transistor; and a second capacitance circuit electrically connected between the collector of the first transistor and the base of the second transistor.
    Type: Application
    Filed: December 29, 2022
    Publication date: May 4, 2023
    Inventors: Satoshi TANAKA, Satoshi ARAYASHIKI, Satoshi GOTO, Yusuke TANAKA
  • Patent number: 11621733
    Abstract: A radio-frequency circuit is used in simultaneous transfer of a radio-frequency signal of 4G and a radio-frequency signal of 5G, and includes a first transfer circuit that selectively receives the 4G radio-frequency signal or the 5G radio-frequency signal, and transfers a radio-frequency signal of a first communication band including a first transmission band and a first reception band and a radio-frequency signal of a second communication band including a second transmission band and a second reception band. The first and second transmission bands at least partially overlap. The first transfer circuit includes a first power amplifier that amplifies transmission signals of the first and second communication bands, and a first transmission filter that has a first passband including the first and second transmission bands, and passes the transmission signals of the first and second communication bands output from the first power amplifier.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: April 4, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Atsushi Ono, Satoshi Tanaka, Hirotsugu Mori
  • Patent number: 11616479
    Abstract: A power amplifier apparatus includes a semiconductor substrate, a plurality of first transistors on the semiconductor substrate, a plurality of second transistors, at least one collector terminal electrically connected to collectors of the plurality of first transistors, a first inductor having a first end electrically connected to the collector terminal and a second end electrically connected to a power supply potential, at least one emitter terminal electrically connected to emitters of the plurality of second transistors and adjacent to the collector terminal in a second direction, a second inductor having a first end electrically connected to the emitter terminal and a second end electrically connected to a reference potential, and at least one capacitor having a first end electrically connected to the collectors of the plurality of first transistors and a second end electrically connected to the emitters of the plurality of second transistors.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: March 28, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Toshikazu Terashima, Fumio Harima, Makoto Itou, Satoshi Tanaka, Kazuo Watanabe, Satoshi Arayashiki, Chikara Yoshida
  • Publication number: 20230087060
    Abstract: A communication device may execute a wireless communication of object data with a mobile device via a first target network using a second type of interface after executing a sending process of sending a wireless setting, for causing the mobile device to belong to the first target network, to the mobile device using a first type of interface in a case where the communication device is determined as currently belonging to the first target network. The communication device may execute the wireless communication of the object data with the mobile device via a second target network using the second type of interface after executing a specific process of causing both the communication device and the mobile device to belong to the second target network in a case where the communication device is determined as currently not belonging to the target network.
    Type: Application
    Filed: October 31, 2022
    Publication date: March 23, 2023
    Inventors: Takanobu Suzuki, Hirotaka Asakura, Munehisa Matsuda, Satoshi Tanaka
  • Patent number: 11611361
    Abstract: A feed line connects an RFIC and a radiating element. A baseband ground plane (BB ground) is connected to a ground terminal of a BBIC. A radio frequency ground plane (RF ground) is placed in such a manner as to overlap the BB ground. The RF ground serves as a return path of the feed line. A first inter-ground connection circuit connects the BB ground and the RF ground. Furthermore, a second inter-ground connection circuit connects the BB ground and the RF ground. Connecting parts between these grounds and the second inter-ground connection circuit are arranged closer to the edges of these grounds than connecting parts between these grounds and the first inter-ground connection circuit. The connecting part between the ground and the second inter-ground connection circuit is placed on one side of a certain imaginary straight line that passes substantially the geometric center of the ground.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: March 21, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kazunari Kawahata, Ryuken Mizunuma, Hideki Ueda, Satoshi Tanaka, Masashi Omuro, Yasuhisa Yamamoto
  • Patent number: 11611942
    Abstract: A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: March 21, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Kiichiro Takenaka, Takayuki Tsutsui, Taizo Yamawaki, Shun Imai
  • Publication number: 20230077966
    Abstract: A conductive substrate includes a base material and a conductive layer arranged on the base material, in which the conductive layer has a conductive thin wire part containing a metal and a transparent insulating part containing no metal, the transparent insulating part being adjacent to the conductive thin wire part, and the conductive layer contains a compound represented by Formula (1).
    Type: Application
    Filed: July 11, 2022
    Publication date: March 16, 2023
    Applicant: FUJIFILM Corporation
    Inventor: Satoshi TANAKA
  • Patent number: 11606066
    Abstract: A power amplifier circuit includes a first amplifier that amplifies an input signal and outputs an output signal; a second amplifier that, in accordance with a control signal, amplifies a signal corresponding to the input signal, generates a signal having an opposite phase to that of the output signal, and adds the signal to the output signal; and a control circuit that supplies the control signal to the second amplifier. The control circuit outputs the control signal so that during operation of the power amplifier circuit in a first power mode, a gain of the second amplifier is not less than zero and less than a predetermined level and during operation in a second power mode lower than the first power mode in output power level, a gain of the second amplifier is not less than the predetermined level and less than a gain of the first amplifier.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: March 14, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Satoshi Arayashiki, Kazuo Watanabe
  • Patent number: 11601102
    Abstract: A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor disposed on the semiconductor substrate and configured to supply a bias current based on a first current which is a part of a control current to the first transistor; a third transistor disposed on the semiconductor substrate and having a collector configured to be supplied with a second current which is a part of the control current and an emitter configured to output a third current based on the second current; a first bump electrically connected to an emitter of the first transistor and disposed so as to overlap a first disposition area in which the first transistor is disposed in plan view of the semiconductor substrate; and a second bump disposed so as to overlap a second disposition area in which the third transistor is disposed in the plan view.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: March 7, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hiroaki Tokuya, Hideyuki Sato, Fumio Harima, Kenichi Shimamoto, Satoshi Tanaka, Takayuki Kawano, Ryoki Shikishima, Atsushi Kurokawa
  • Patent number: 11591252
    Abstract: A production method and others according to the present embodiment are provided with a structure for effectively preventing occurrence of accidental spiking during drawing of a preform. In order to control the residual He-concentration in the center part of the preform, a transparent glass rod that has a predetermined outer diameter and is already sintered but is not doped with an alkali metal yet is annealed in in the atmosphere not containing He gas for an annealing time determined by referring to result data in which the relationship between the annealing time and the residual He-concentration is previously recorded for each outer diameter. In the result data, actually measured data of the residual He-concentration in a produced optical fiber preform and the annealing time are accumulated as annealing treatment results.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: February 28, 2023
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takumi Yonemura, Noboru Yamazaki, Satoshi Tanaka
  • Patent number: 11588442
    Abstract: A power amplifier circuit includes a first power supply terminal electrically connected to a first power amplifier; a second power supply terminal electrically connected to a second power amplifier subsequent to the first power amplifier; a first external power supply line configured to electrically connect a power supply circuit configured to output a power supply potential corresponding to an amplitude level of a high-frequency input signal and the first power supply terminal; and a second external power supply line configured to electrically connect the power supply circuit and the second power supply terminal. An inductance value of the first external power supply line is higher than an inductance value of the second external power supply line.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: February 21, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Satoshi Arayashiki, Kenji Mukai
  • Patent number: 11581106
    Abstract: A conductive substrate includes a base material and a conductive layer arranged on the base material, in which the conductive layer has a conductive thin wire part containing a metal and a transparent insulating part containing no metal, the transparent insulating part being adjacent to the conductive thin wire part, and the conductive layer contains a compound represented by Formula (1).
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: February 14, 2023
    Assignee: FUJIFILM Corporation
    Inventor: Satoshi Tanaka
  • Patent number: 11582592
    Abstract: A communication device may include a first type of interface and a second type of interface. The communication device may execute the communication of object data with a mobile device using the second type of interface after executing a specific process for causing the communication device to shift to a communication-enabled state, in a case where it is determined that the communication device is not currently in the communication-enabled state. Also, the communication device may execute the communication of the object data with the mobile device using the second type of interface without executing the specific process, in a case where it is determined that the communication device is currently in the communication-enabled state.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: February 14, 2023
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Takanobu Suzuki, Hirotaka Asakura, Munehisa Matsuda, Satoshi Tanaka
  • Publication number: 20230035309
    Abstract: A communication system is configured to use a pulse width modulation signal as transmission code among a plurality of nodes connected to a communication line. A master node includes a transmission transistor connected to the communication line, a detector configured to detect a variation in current during the on-period of the transmission transistor, and a communication circuit configured to determine the off-timing of the transmission transistor based on the timing of occurrence of the variation in current (i.e., the on-timing of a second transmission transistor provided in a slave node). For example, the communication circuit can be configured to determine the off-timing of the transmission transistor such that the simultaneously-on period TB of the transmission transistor and the second transmission transistor fulfills TB=(2n?1)/2f, where f is the frequency of EMI noise.
    Type: Application
    Filed: October 16, 2020
    Publication date: February 2, 2023
    Inventors: Shinya Masuda, Satoshi Tanaka, Toru Mukai, Hiroki Yamakami
  • Patent number: 11569787
    Abstract: Provided is a power amplification module that includes: a first transistor, a first signal being inputted to a base thereof; a second transistor, the first signal being inputted to a base thereof and a collector thereof being connected to a collector of the first transistor; a first resistor, a first bias current being supplied to one end thereof and another end thereof being connected to the base of the first transistor; a second resistor, one end thereof being connected to the one end of the first resistor and another end thereof being connected to the base of the second transistor; and a third resistor, a second bias current being supplied to one end thereof and another end thereof being connected to the base of the second transistor.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: January 31, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Arayashiki, Satoshi Goto, Satoshi Tanaka, Yasuhisa Yamamoto