Patents by Inventor Satoshi Tanaka

Satoshi Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11569786
    Abstract: A power amplifier circuit includes an amplifier transistor having a base, a collector, a bias circuit, and a first resistance element connected between the base of the amplifier transistor and the bias circuit. The bias circuit includes a voltage generation circuit, a first transistor having a base to which a first direct-current voltage is supplied, and an emitter from which the bias current or voltage is supplied, a second transistor having a base to which a second direct-current voltage is supplied, and an emitter connected to the emitter of the first transistor, a signal supply circuit disposed between the base of the amplifier transistor and the base of the second transistor, and an impedance circuit disposed between the base of the first transistor and the base of the second transistor.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: January 31, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuri Honda, Fumio Harima, Satoshi Tanaka
  • Patent number: 11569787
    Abstract: Provided is a power amplification module that includes: a first transistor, a first signal being inputted to a base thereof; a second transistor, the first signal being inputted to a base thereof and a collector thereof being connected to a collector of the first transistor; a first resistor, a first bias current being supplied to one end thereof and another end thereof being connected to the base of the first transistor; a second resistor, one end thereof being connected to the one end of the first resistor and another end thereof being connected to the base of the second transistor; and a third resistor, a second bias current being supplied to one end thereof and another end thereof being connected to the base of the second transistor.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: January 31, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Arayashiki, Satoshi Goto, Satoshi Tanaka, Yasuhisa Yamamoto
  • Patent number: 11557664
    Abstract: A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: January 17, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Takayuki Tsutsui, Satoshi Tanaka
  • Patent number: 11558014
    Abstract: A power amplifier circuit includes a first transistor having an emitter electrically connected to a common potential, a base to which a first high-frequency signal is input, and a collector from which a third high-frequency signal is output; a second transistor having an emitter electrically connected to the common potential, a base to which a second high-frequency signal is input, and a collector from which a fourth high-frequency signal is output; a first capacitance circuit electrically connected between the collector of the second transistor and the base of the first transistor; and a second capacitance circuit electrically connected between the collector of the first transistor and the base of the second transistor.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: January 17, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Satoshi Arayashiki, Satoshi Goto, Yusuke Tanaka
  • Patent number: 11552601
    Abstract: A power amplifier circuit includes an input-stage power amplifier configured to receive a radio-frequency input signal, an output-stage power amplifier configured to output an amplified radio-frequency output signal, and an intermediate-stage power amplifier disposed between the input-stage power amplifier and the output-stage power amplifier. The intermediate-stage power amplifier includes a first transistor, a second transistor, and a capacitor having a first end connected to an emitter of the first transistor and a second end connected to a collector of the second transistor. The intermediate-stage power amplifier receives a signal at a base of the second transistor thereof and outputs an amplified signal from a collector of the first transistor thereof.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: January 10, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shingo Yanagihara, Satoshi Tanaka
  • Patent number: 11549807
    Abstract: A pattern according to an embodiment includes first and second line patterns, each of the first and second line patterns extends in a direction intersecting a <111> direction and has a side surface, the side surface has at least one {111} crystal plane, the side surface of the first line pattern has a first roughness, and the side surface of the second line pattern has a second roughness larger than the first roughness.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: January 10, 2023
    Assignee: KIOXIA Corporation
    Inventors: Susumu Iida, Satoshi Tanaka, Takayuki Uchiyama
  • Patent number: 11545944
    Abstract: A power amplifier circuit includes a power amplifier including a first transistor having a first terminal connected to a reference potential, a second terminal to which a first current and a radio-frequency signal are input, and a third terminal connected to a first power supply potential via a first inductor; a capacitor connected to the third terminal of the first transistor; a second transistor including a first terminal connected to the capacitor and the reference potential via a second inductor, a second terminal to which a second current is input and is connected to the reference potential, and a third terminal connected to the first power supply potential via a third inductor and outputs signal; and an adjustment circuit that outputs a third current corresponding to the first power supply potential or a second power supply potential to the second terminal of the second transistor.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: January 3, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Jun Enomoto, Kazuo Watanabe, Satoshi Tanaka, Yusuke Tanaka, Makoto Ito
  • Patent number: 11537726
    Abstract: A secret computation system is a secret computation system for performing computation while keeping data concealed, and comprises a cyphertext generation device that generates cyphertext by encrypting the data, a secret computation device that generates encrypted basic statistics by performing secret computation of predetermined basic statistics using the cyphertext while keeping the cyphertext concealed, and a computation device that generates decrypted basic statistics by decrypting the encrypted basic statistics and performs predetermined computation using the decrypted basic statistics.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: December 27, 2022
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Satoshi Tanaka, Ryo Kikuchi, Koji Chida
  • Patent number: 11535060
    Abstract: A heavy duty pneumatic tire in which occurrence of uneven wear is inhibited is provided. In the tire, each shoulder land portion includes a groove wall portion forming a wall of a shoulder circumferential groove, and a cap portion located outward of the groove wall portion in an axial direction. A wear resistance index of the groove wall portion is lower than a wear resistance index of the cap portion. A ratio of a distance in the axial direction from an outer edge of the shoulder circumferential groove to a boundary between the groove wall portion and the cap portion on an outer surface of the shoulder land portion, to a width in the axial direction of the shoulder land portion, is not less than 20% and not greater than 30%.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: December 27, 2022
    Assignee: SUMITOMO RUBBER INDUSTRIES, LTD.
    Inventors: Satoko Tsujibayashi, Yoshiyuki Takada, Satoshi Tanaka
  • Patent number: 11528012
    Abstract: An active balun circuit includes first and second transistors having emitters electrically coupled to each other and configured to output differential signals and a circuit element coupled between the connection point of the emitter of the first transistor and the emitter of the second transistor and a reference potential. The impedance of the circuit element at a particular frequency of the input signal appears significantly larger than impedances at other frequencies. An input signal from an input terminal is inputted to the base of the first transistor. The reference potential is applied to the base of the second transistor. A supply voltage is applied to the collector of the first transistor and the collector of the second transistor. A signal from the collector of the first transistor and a signal from the collector of the second transistor are outputted as the differential signals.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: December 13, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takayuki Tsutsui, Satoshi Tanaka, Kiichiro Takenaka, Masatoshi Hase
  • Patent number: 11528073
    Abstract: A communication terminal capable of at least millimeter-wave communication and microwave communication is provided. The communication terminal includes a repeater that relays communication between a first communication terminal and a second communication terminal by using millimeter-wave communication. Such a communication terminal is capable of maintaining good millimeter-wave communication between terminals.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: December 13, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Ryuken Mizunuma, Satoshi Tanaka, Yasuhisa Yamamoto, Akiko Itabashi
  • Patent number: 11515840
    Abstract: The present disclosure is to improve the power added efficiency of a power amplifier at high output power. The power amplifier includes: a first capacitor with a radio frequency signal input to one end thereof; a first transistor whose base is connected to the other end of the first capacitor to amplify the radio frequency signal; a bias circuit for supplying bias to the base of the first transistor; and a second capacitor with one end connected to the base of the first transistor and the other end connected to the emitter of the first transistor.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: November 29, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kazuo Watanabe, Satoshi Tanaka, Norio Hayashi, Kazuma Sugiura
  • Patent number: 11516644
    Abstract: A communication device may execute a wireless communication of object data with a mobile device via a first target network using a second type of interface after executing a sending process of sending a wireless setting, for causing the mobile device to belong to the first target network, to the mobile device using a first type of interface in a case where the communication device is determined as currently belonging to the first target network. The communication device may execute the wireless communication of the object data with the mobile device via a second target network using the second type of interface after executing a specific process of causing both the communication device and the mobile device to belong to the second target network in a case where the communication device is determined as currently not belonging to the target network.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: November 29, 2022
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Takanobu Suzuki, Hirotaka Asakura, Munehisa Matsuda, Satoshi Tanaka
  • Publication number: 20220357907
    Abstract: A function executing device is configured to send a wireless identifier to a communication device via a first type of wireless communication interface for setting up a wireless connection. The function executing device is configured to determine whether the function executing device is in an error state and, if not, to establish the wireless connection via a second type of wireless communication interface. The function executing device operates in a parent state in the wireless connection. Additionally, print data may be received from the communication device. However, if the function executing device is in an error state the wireless connection is not established via the second type of wireless communication interface.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Takanobu Suzuki, Hirotaka Asakura, Munehisa Matsuda, Satoshi Tanaka
  • Patent number: 11496178
    Abstract: A high-frequency module includes a transmission signal amplifier that outputs a transmission signal to an antenna terminal side; a reception signal amplifier that amplifies a reception signal supplied from an antenna terminal; a switch that selectively connects the antenna terminal to either an output of the transmission signal amplifier or an input of the reception signal amplifier; and a directional coupler that is provided on a transmission signal path and detects a signal level of the transmission signal. The transmission signal amplifier is controlled by a first control signal supplied from a first control circuit. The reception signal amplifier is controlled by a second control signal supplied from a second control circuit. The switch is controlled by a switch control signal supplied from the first control circuit. The directional coupler is controlled by a coupler control signal supplied from the first control circuit.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: November 8, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Sakurai, Satoshi Arayashiki, Satoshi Tanaka, Kyoichi Hirayama, Tomohito Ito, Kenta Kurahashi
  • Patent number: 11496163
    Abstract: A radio frequency circuit includes: a first power amplifier capable of amplifying a first radio frequency signal and a second radio frequency signal each having a different frequency; and a second power amplifier capable of amplifying the second radio frequency signal. In a case where the first radio frequency signal and the second radio frequency signal are simultaneously transmitted, (i) under a condition that a sum of a bandwidth of the first radio frequency signal and a bandwidth of the second radio frequency signal is broader than or equal to a predetermined bandwidth, the first radio frequency signal is amplified by the first power amplifier, and the second radio frequency signal is amplified by the second power amplifier, and (ii) under a condition that the sum is narrower than the predetermined bandwidth, the first radio frequency signal and the second radio frequency signal are amplified by the first power amplifier.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: November 8, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Hirotsugu Mori
  • Patent number: 11496168
    Abstract: A radio frequency circuit includes an amplifier capable of amplifying a first radio frequency signal and a second radio frequency signal that has a frequency different from a frequency of the first radio frequency signal. Here, the amplifier uses a first power-supply voltage to amplify one of the first radio frequency signal and the second radio frequency signal and uses a second power-supply voltage to amplify both the first radio frequency signal and the second radio frequency signal together. A value of the second power-supply voltage is greater than a value of the first power-supply voltage.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: November 8, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Hirotsugu Mori, Hidenori Obiya, Morio Takeuchi
  • Publication number: 20220340196
    Abstract: A steering device according to one aspect of the disclosure includes: a speed reducer configured to decelerate a rotational power input from one surface side while increasing a torque and output rotation from an output section disposed on the other surface side; a motor provided on the one surface side and configured to input the rotational power to the speed reducer; and a control device for controlling the motor. The motor includes a rotor for generating the rotational power. The rotor includes a rotor output shaft disposed coaxially with an output axis of the output section. The motor inputs the rotational power from one end side of the rotor output shaft to the speed reducer. The control device is disposed on the other end side of the rotor output shaft coaxially with the rotor output shaft and includes a sensing unit for sensing rotation of the rotor.
    Type: Application
    Filed: April 18, 2022
    Publication date: October 27, 2022
    Inventors: Satoshi TANAKA, Stefan KUBINA
  • Patent number: 11476807
    Abstract: A power amplifier module includes a first amplifier circuit that amplifies a radio frequency signal with a first gain corresponding to a first control signal to generate a first amplified signal; a second amplifier circuit that amplifies the first amplified signal with a second gain corresponding to a second control signal to generate a second amplified signal; and a control unit that generates the first control signal and the second control signal. The second control signal is a control signal for increasing a power-supply voltage for the second amplifier circuit as a peak-to-average power ratio of the radio frequency signal increases. The first control signal is a control signal for controlling the first gain of the first amplifier circuit so that a variation in the second gain involved in a variation in the power-supply voltage for the second amplifier circuit is compensated for.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: October 18, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shigeki Koya, Takayuki Tsutsui, Yasunari Umemoto, Isao Obu, Satoshi Tanaka
  • Patent number: 11469715
    Abstract: A power amplifier circuit includes first and second bias circuits configured to provide first and second biases, respectively, a first transistor having an emitter connected to a reference potential, a base configured to receive the first bias via a first resistor and receive a radio-frequency input signal via a first capacitor, and a collector configured to output an amplified radio-frequency signal, a second transistor having a base connected to the reference potential via a second capacitor and configured to receive the second bias via a second resistor, an emitter configured to receive the radio-frequency signal, and a collector connected to a power supply potential via a third inductor and configured to output a radio-frequency output signal, and an impedance circuit having a first end connected to an output section of the second bias circuit and configured to apply an alternating-current signal to a path extending from the second bias circuit.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: October 11, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Jun Enomoto, Kazuo Watanabe, Satoshi Tanaka, Yusuke Tanaka, Makoto Itou