Abstract: A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory cell transistors present in the identical first direction; a plurality of bit lines commonly coupling the drains of the plural memory cell transistors present in a identical second direction intersecting the first direction; a first transistor having a drain coupled to the source line; a second transistor having a drain coupled to a source of the first transistor, a gate coupled to the word line and a source grounded; and a control line commonly coupling the gates of the plural first transistors.

Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Abstract: A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory cell transistors present in the identical first direction; a plurality of bit lines commonly coupling the drains of the plural memory cell transistors present in a identical second direction intersecting the first direction; a first transistor having a drain coupled to the source line; a second transistor having a drain coupled to a source of the first transistor, a gate coupled to the word line and a source grounded; and a control line commonly coupling the gates of the plural first transistors.

Abstract: A memory system is provided including forming a memory gate stack having a charge trap layer over a semiconductor substrate, forming a protection layer to cover the memory gate stack, and forming a protection enclosure for the charge trap layer with the protection layer and the memory gate stack.

Abstract: A nonvolatile semiconductor memory including a memory cell array of memory cells arranged in a matrix, each of which includes a selective transistor and a memory cell transistor; the first column decoder for controlling the potentials of the bit lines and the source lines; the first row decoder for controlling the potential of the first word lines; the second row decoder for controlling the potential of the second word lines; and the second column decoder. The first column decoder includes a circuit whose withstand voltage is lower than the first row decoder and the second column decoder, and the second row decoder includes a circuit whose withstand voltage is lower than the first row decoder and the second column decoder.

Abstract: A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory cell transistors present in the identical first direction; a plurality of bit lines commonly coupling the drains of the plural memory cell transistors present in a identical second direction intersecting the first direction; a first transistor having a drain coupled to the source line; a second transistor having a drain coupled to a source of the first transistor, a gate coupled to the word line and a source grounded; and a control line commonly coupling the gates of the plural first transistors.

Abstract: A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory cell transistors present in the identical first direction; a plurality of bit lines commonly coupling the drains of the plural memory cell transistors present in a identical second direction intersecting the first direction; a first transistor having a drain coupled to the source line; a second transistor having a drain coupled to a source of the first transistor, a gate coupled to the word line and a source grounded; and a control line commonly coupling the gates of the plural first transistors.

Abstract: A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory cell transistors present in the identical first direction; a plurality of bit lines commonly coupling the drains of the plural memory cell transistors present in a identical second direction intersecting the first direction; a first transistor having a drain coupled to the source line; a second transistor having a drain coupled to a source of the first transistor, a gate coupled to the word line and a source grounded; and a control line commonly coupling the gates of the plural first transistors.

Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Abstract: A semiconductor device includes a first memory cell which includes a first memory transistor and a first selector transistor. The semiconductor device further includes a second memory cell which includes a second memory transistor and a second selector transistor. The semiconductor device further includes a first word line electrically coupled to a gate electrode of the first memory transistor and to a gate electrode of the second selector transistor, and a second word line electrically coupled to a gate electrode of the second memory transistor and to a gate electrode of the first selector transistor. The semiconductor device further includes a first source line electrically coupled to a source region of the first memory transistor and to a source region of the second memory transistor.

Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Abstract: A semiconductor device includes a first memory cell which includes a first memory transistor and a first selector transistor. The semiconductor device further includes a second memory cell which includes a second memory transistor and a second selector transistor. The semiconductor device further includes a first word line electrically coupled to a gate electrode of the first memory transistor and to a gate electrode of the second selector transistor, and a second word line electrically coupled to a gate electrode of the second memory transistor and to a gate electrode of the first selector transistor. The semiconductor device further includes a first source line electrically coupled to a source region of the first memory transistor and to a source region of the second memory transistor.

Abstract: A memory device (100) may include a substrate (110), a dielectric layer (210) formed on the substrate (110) and a charge storage element (220) formed on the dielectric layer (210). The memory device (100) may also include an inter-gate dielectric (230) formed on the charge storage element (220), a barrier layer (240) formed on the inter-gate dielectric (230) and a control gate (250) formed on the barrier layer (240). The barrier layer (240) prevents reaction between the control gate (250) and the inter-gate dielectric (230).

Abstract: Embodiments of the present invention disclose a method of utilizing a flash memory array to decrease programming time while maintaining sufficient read speeds. An array of cells is programmed and read in pages that are oriented in the column direction, parallel to the bit lines in the array. An erased cell in the present invention is a cell in the “off” state. According to the present invention a cell is programmed by lowering the threshold voltage of the cell, thereby turning the cell “on.” An array of cells is programmed read in a sector-by-sector method, wherein a sector consists of units situated diagonally adjacent to each other, and a unit consists of multiple parallel column-oriented pages.

Abstract: A multiple dual bit integrated circuit system is provided that includes forming first address lines in a semiconductor substrate and forming a charge-trapping layer over the semiconductor substrate. A semiconductor layer is formed over the charge-trapping layer and second address lines are formed in the semiconductor layer to form a plurality of dual bit locations.

Abstract: An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.

Abstract: A device includes a substrate and multiple wells formed over the substrate and isolated from one another by dielectric trenches. The device further includes multiple memory elements formed over the wells, each of the memory elements extending approximately perpendicular to the wells and including a material doped with n-type impurities. The device also includes multiple source/drain regions, each source/drain region formed within one of multiple trenches and inside one of the plurality of wells between a pair of the memory elements, each of the source/drain regions implanted with p-type impurities. The device further includes a first substrate contact formed in a first one of the multiple trenches through a first one of the wells into the substrate and a second substrate contact formed in a second one of the multiple trenches through a second one of the wells into the substrate.

Abstract: A semiconductor device includes: a memory cell transistor which has a floating gate, a control gate, and a source and a drain formed in a semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein the source of the selecting transistor is connected to the drain of the memory cell transistor, the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the first impurity diffusion layer, and an N-type third impurity diffusion layer which is shallower than the second impurity diffusion layer, and an impurity density of the second impurity diffusion layer is lower than that of the third impurity diffusion layer.

Abstract: A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory cell transistors present in the identical first direction; a plurality of bit lines commonly coupling the drains of the plural memory cell transistors present in a identical second direction intersecting the first direction; a first transistor having a drain coupled to the source line; a second transistor having a drain coupled to a source of the first transistor, a gate coupled to the word line and a source grounded; and a control line commonly coupling the gates of the plural first transistors.

Abstract: A nonvolatile semiconductor memory including a memory cell array of memory cells arranged in a matrix, each of which includes a selective transistor and a memory cell transistor; the first column decoder for controlling the potentials of the bit lines and the source lines; the first row decoder for controlling the potential of the first word lines; the second row decoder for controlling the potential of the second word lines; and the second column decoder. The first column decoder includes a circuit whose withstand voltage is lower than the first row decoder and the second column decoder, and the second row decoder includes a circuit whose withstand voltage is lower than the first row decoder and the second column decoder.