Abstract: The invention provides a class B output stage for an amplifier, more specifically an integrated circuit amplifier for low power, low voltage application, such as a hearing aid amplifier, that is of class B type with consequent negligible quiescent power dissipation, but which avoids the input voltage deadband of conventional class B stages that results in cross-over distortion. The stage uses a bipolar transistor and a field transistor connected in series. The field effect transistor has a gate-source pinch-off voltage that is approximately equal to the base-emitter voltage of the bipolar transistor, so that they are alternately "on" as the input voltage swings over its full value. In a preferred embodiment the bipolar transistor is an npn type while the field effect transistor is a bipolar compatible p-channel junction field effect transistor (JFET) with pinch-off voltage as close as possible but just less than the base emitter voltage of the bipolar transistor.

Abstract: The invention provides a new structure for a subsurface junction field effect transistor (SJFET) and a new process for its fabrication, the process being especially compatible with existing processes for the fabrication of bipolar devices. Spaced zones of p.sup.+ type are diffused into an n-type epitaxial layer to terminate the channel and connect to source and drain terminals. Spaced zones of n.sup.+ type are diffused into the epitaxial layer to define the channel width. The corresponding zones for the bipolar device can be formed at the same time. A passivating layer of silicon dioxide is applied and the subsurface p-type channel formed by ion implantation to leave a thin n-type layer between the channel and the silicon dioxide layer. Upon application of a metal layer over the silicon dioxide layer in the neighborhood of the channel, and its connection to the back gate terminal, a stable electron accumulation layer forms at the surface of the n-type layer which interfaces with the silicon dioxide layer.

Abstract: A current mirror biasing arrangement for an electronic circuit, particularly one intended for an integrated circuit employs a current mirror constituted by series connected pnp and npn transistors having their collectors connected together. A pair of series-connected field effect transistors (FET) connected between a voltage source and ground have their gates connected to the emitter and collector of the pnp transistor and their junction to the pnp transistor base. The pnp transistors to be biased have their bases connected to the said FET junction. The gate current of the operative FET can be made negligible so that substantially perfect matching is obtained between the npn transistor current and the "mirror" biasing current. Preferably the FET are of subsurface junction type, their low pinch-off voltage and low gate current making them particularly suitable for low voltage application.