Abstract: A power semiconductor device includes a semiconductor die with a power transistor on a semiconductor substrate, a plurality of wiring layers vertically spaced apart from one another and the transistor, and a plurality of conductive bumps on each wire of the wiring layer spaced farthest from the substrate. Each wire of the layer closest to the substrate is electrically connected to a terminal of the transistor. The wires of the layer spaced farthest from the substrate extend in generally parallel lines and are electrically connected to a terminal of the transistor through each underlying layer. An additional metal layer having a thickness of at least 50 ?m is connected to the die so that contact regions of the additional metal layer are electrically connected to the bumps of the die.

Abstract: A bonding plate forms high-performance, low-resistance interconnections between integrated circuit die and an electronic package lead frame. The bonding plate is made from copper, aluminum, or metalized silicon and is processed using standard semiconductor fabrication techniques to apply solder bumps and, optionally, copper pillars. The bonding plates are singulated from a wafer and applied to the die package using standard pick-and-place and solder reflow equipment and processes. This achieves high performance interconnect at low cost without the need for specialized tooling.