Abstract: Embodiments of the invention provide a machine that blends liquids and/or shaves ice. The machine includes a motor and a control system with an integrated power factor correction circuit and a drive circuit. The integrated power factor correction circuit receives input power from a mains power line, reduces noise transmitted to the mains power line, and provides a boosted, regulated output voltage. The drive circuit is connected to the motor and uses the regulated output voltage in order to control an effective voltage applied to the motor substantially independent of the voltage and frequency of the input power.

Abstract: Embodiments of the invention provide a machine that blends liquids and/or shaves ice. The machine includes a motor and a control system with an integrated power factor correction circuit and a drive circuit. The integrated power factor correction circuit receives input power from a mains power line, reduces noise transmitted to the mains power line, and provides a boosted, regulated output voltage. The drive circuit is connected to the motor and uses the regulated output voltage in order to control an effective voltage applied to the motor substantially independent of the voltage and frequency of the input power.

Abstract: A system for sharing of switching losses of parallel transistors is disclosed. The system includes a plurality of switching transistors connected in parallel for providing a current to a load. A pulse generator provides pulse width modulated pulse cycles in response to the load current each pulse cycle having a pulse signal. An alternate selector is responsive to said pulse cycles, and provides the pulse cycles to the transistors, such that for each pulse cycle a predetermined transistor turns ON substantially prior to the other transistors, dissipating substantially all the turn ON losses, and a predetermined transistor turns OFF substantially later than other transistors, dissipating substantially all the turn OFF losses.

Abstract: A twenty four bit digital-to-analog converter comprising three eight bit digital-to-analog converters. The outputs of the two least significant converters are proportioned and summed together into one amplifier to form a sixteen bit converter. The most significant converter is fed to a separate amplifier. The output of the two amplifiers is summed into a square-root amplifier through various analog switches and summing resistors. Gains at the input and output of the square-root amplifier are altered according to the input level of the digital-to-analog converter in order to optimize the dynamic range and gain requirements.