Abstract: A semiconductor device is disclosed having improved vertical gain symmetry, and which includes thick, lightly-doped regions which are dielectrically isolated and provided by at least two separately processed semiconductor wafers which are bonded together and further processed to provide the finished device. Alternate embodiments include buried layers exhibiting very low resistance. Further alternate embodiments provide high voltage and/or high current devices which are fabricated together with low-power circuitry as an integrated circuit.

Abstract: A new diode structure is provided by bonding two semiconductor materials together having a low capacitance, a large contact area and mechanical ruggedness. The cross-sectional area of at least one of the semiconductor materials is reduced in the region of the bond resulting in a structure with either an hourglass or truncated hourglass-like cross-section. A diode PN junction is contained in the neighborhood of the area of reduced cross section. The diode so constructed provides a sufficient spacing between the unbonded semiconductor regions to reduce total packaged diode capacitance without introducing a spacer layer. The diode is processed to limit the area of the PN junction formed therein to the region of the bonding between the semiconductor materials, without limiting the metallized contact area, further controlling the diode capacitance as well as other electrical characteristics.

Abstract: A method for processing at least two semiconductor wafers for producing a partially processed semiconductor substrate which can be subsequently further processed utilizing conventional planar semiconductor processing techniques to achieve a complementary semiconductor structure in which a plurality of matched semiconductor elements can be formed. An embedded silicide layer in the bonded semiconductor substrate acts as a conduit for horizontally dispersing dopant during the diffusion process. The dopant subsequently up-diffuses into an adjacent silicon region forming generally uniform and shallow, buried layer regions.

Abstract: A process for fabricating a semiconductor device by forming a diffusion region in a first semiconductor wafer and bonding the surface of the first semiconductor wafer having the diffused region to a second semiconductor wafer to form a low resistance buried layer. The process includes further diffusion to provide an external electrical contact with the buried layer. Further enhancements are provided by selectively forming voids and/or selectively applying materials of greater and lesser conductivity on at least one of the semiconductor wafers before bonding, forming complex internal semiconductor structures in the bonded wafer structures.

Abstract: A vertical IGFET comprising a substantially planar silicon wafer with a source electrode on one major surface and a drain electrode on the opposite major surface is disclosed. An insulated gate electrode, which includes a conductive finger portion surrounded by an insulating layer, is internally disposed in the silicon wafer such that a predetermined voltage applied to the gate electrode will regulate a current flow between the source and drain electrodes. The device is fabricated utilizing an epitaxial lateral overgrowth technique for depositing monocrystalline silicon over the insulated gate which is disposed on a silicon substrate.

Abstract: A monocrystalline silicon layer is formed on a mask layer on a semiconductor substrate. An apertured mask layer is disposed on the substrate, and an epitaxial layer is then grown by a two-step deposition/etching cycle. By repeating the deposition/etching cycle a predetermined number of times, monocrystalline silicon will be grown from the substrate surface, through the mask aperture, and over the mask layer.

Abstract: A monocrystalline silicon layer is formed on a mask layer on a semiconductor substrate. An apertured mask layer is disposed on the substrate, and an epitaxial layer is then grown by a two-step deposition/etching cycle. By repeating the deposition/etching cycle a predetermined number of times, monocrystalline silicon will be grown from the substrate surface, through the mask aperture, and over the mask layer.

Abstract: A vertical IGFET comprising a substantially planar silicon wafer with a source electrode on one major surface and a drain electrode on the opposite major surface is disclosed. An insulated gate electrode, which includes a conductive finger portion surrounded by an insulating layer, is internally disposed in the silicon wafer such that a predetermined voltage applied to the gate electrode will regulate a current flow between the source and drain electrodes. The device is fabricated utilizing an epitaxial lateral overgrowth technique for depositing monocrystalline silicon over the insulated gate which is disposed on a silicon substrate.

Abstract: A method for forming closely spaced conductors suitable for use, for example, in CCD's and MESFET's is described utilizing an edge diffusion technique to convert exposed edge portions of a polycrystalline silicon layer to a non-etchable form. The converted portions are precisely and accurately formed to serve as spacers, thereby defining a narrow gap between adjacent conductive lines.