Patents by Inventor Scott D. Rodgers

Scott D. Rodgers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140281376
    Abstract: In an embodiment, a processor includes a binary translation (BT) container having code to generate a binary translation of a first code segment and to store the binary translation in a translation cache, a host entity logic to manage the BT container and to identify the first code segment, and protection logic to isolate the BT container from a software stack. In this way, the BT container is configured to be transparent to the software stack. Other embodiments are described and claimed.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 18, 2014
    Inventors: Koichi Yamada, Palanivel Rajan Shanmugavelayutham, Scott D. Rodgers, Barry E. Huntley, James D. Beaney, JR., Boaz Tamir
  • Patent number: 8793470
    Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 29, 2014
    Assignee: Intel Corporation
    Inventors: James S. Coke, Peter J. Ruscito, Masood Tahir, David B. Jackson, Ves A. Naydenov, Scott D. Rodgers, Bret L. Toll, Frank Binns
  • Publication number: 20140006739
    Abstract: Embodiments of systems, apparatuses, and methods for temporarily allowing access to a lower privilege level from a higher privilege level.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Inventors: Martin G. Dixon, Gilbert Neiger, Robert S. Chappell, Scott D. Rodgers, Barry E. Huntley
  • Publication number: 20130326519
    Abstract: Embodiments of apparatuses and methods for processing virtual machine control structure shadowing are disclosed. In one embodiment, an apparatus includes instruction hardware, execution hardware, and control logic. The instruction hardware is to receive instructions. A first instruction is to transfer the processor from a root mode to a non-root mode. The non-root mode is for executing guest software in a virtual machine, where the processor is the return to root mode upon the detection of a virtual machine exit event. A second instruction is to access a data structure for controlling a virtual machine. The execution hardware is to execute the instructions. The control logic is to cause the processor to access a shadow data structure instead of the data structure, without returning to the root mode for the access to be performed, when the second instruction is executed in the non-root mode.
    Type: Application
    Filed: December 30, 2011
    Publication date: December 5, 2013
    Inventors: Andrew V. Anderson, Gilbert Neiger, Scott D. Rodgers, Lawrence O. Smith, III, Richard A. Uhlig, Steven M. Bennett
  • Publication number: 20130246824
    Abstract: In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.
    Type: Application
    Filed: May 10, 2013
    Publication date: September 19, 2013
    Inventors: Martin G. Dixon, Scott D. Rodgers, Taraneh Bahrami, Stephen H. Gunther, Prashant Sethi, Per Hammarlund
  • Patent number: 8521969
    Abstract: In an embodiment, memory access requests for information stored within a system memory pass through an integrated circuit. The system memory may include a micro-architectural memory region to store instructions and/or data, where the micro-architectural memory region is to be exclusively accessible by a micro-architectural agent The integrated circuit may include memory access director to direct memory access requests to the micro-architectural memory region if the memory access director determines that the memory access request includes a location within the at least one micro-architectural memory region and the micro-architectural agent is operating in a micro-architectural memory region access mode.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: August 27, 2013
    Assignee: Intel Corporation
    Inventors: Martin G. Dixon, Scott D. Rodgers, James P. Held, Bill Alexander, Larry O. Smith, Scott H. Robinson, Sham M. Datta
  • Publication number: 20130219143
    Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.
    Type: Application
    Filed: March 15, 2013
    Publication date: August 22, 2013
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard UhligQ, Lawrence Smith, III, Scott D. Rodgers
  • Publication number: 20130219152
    Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
    Type: Application
    Filed: March 15, 2013
    Publication date: August 22, 2013
    Inventors: James S. Coke, Peter J. Ruscito, Masood Tahir, David B. Jackson, Ves A. Naydenov, Scott D. Rodgers, Bret L. Toll, Frank Binns
  • Publication number: 20130174147
    Abstract: Various embodiments of this disclosure may describe method, apparatus and system for reducing system latency caused by switching memory page permission views between programs while still protecting critical regions of the memory from attacks of malwares. Other embodiments may be disclosed and claimed.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 4, 2013
    Inventors: Ravi L. Sahita, David M. Durham, Gilbert Neiger, Andrew V. Anderson, Scott D. Rodgers
  • Patent number: 8464035
    Abstract: In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: June 11, 2013
    Assignee: Intel Corporation
    Inventors: Martin G. Dixon, Scott D. Rodgers, Taraneh Bahrami, Stephen H. Gunther, Prashant Sethi, Per Hammarlund
  • Patent number: 8402252
    Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
    Type: Grant
    Filed: March 10, 2012
    Date of Patent: March 19, 2013
    Assignee: Intel Corporation
    Inventors: James S. Coke, Peter J. Ruscito, Masood Tahir, David B. Jackson, Ves A. Naydenov, Scott D. Rodgers, Bret L. Toll, Frank Binns
  • Publication number: 20120173852
    Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
    Type: Application
    Filed: March 10, 2012
    Publication date: July 5, 2012
    Inventors: James S. Coke, Peter J. Ruscito, Masood Tahir, David B. Jackson, Ves A. Naydenov, Scott D. Rodgers, Bret L. Toll, Frank Binns
  • Patent number: 8214598
    Abstract: Systems, methods, and apparatus for performing the flushing of a plurality of cache lines and/or the invalidation of a plurality of translation look-aside buffer (TLB) entries is described. In one such method, for flushing a plurality of cache lines of a processor a single instruction including a first field that indicates that the plurality of cache lines of the processor are to be flushed and in response to the single instruction, flushing the plurality of cache lines of the processor.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: July 3, 2012
    Assignee: Intel Corporation
    Inventors: Martin G. Dixon, Scott D. Rodgers
  • Patent number: 8161269
    Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: April 17, 2012
    Assignee: Intel Corporation
    Inventors: James S. Coke, Peter J. Ruscito, Masood Tahir, David B. Jackson, Ves A. Naydenov, Scott D. Rodgers, Bret L. Toll, Frank Binns
  • Publication number: 20110173418
    Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
    Type: Application
    Filed: March 24, 2011
    Publication date: July 14, 2011
    Inventors: James S. Coke, Peter J. Ruscito, Masood Tahir, David B. Jackson, Ves A. Naydenov, Scott D. Rodgers, Bret L. Toll, Frank Binns
  • Publication number: 20110154079
    Abstract: In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.
    Type: Application
    Filed: December 18, 2009
    Publication date: June 23, 2011
    Inventors: Martin G. Dixon, Scott D. Rodgers, Taraneh Bahrami, Stephen H. Gunther, Prashant Sethi, Per Hammarlund
  • Publication number: 20110153952
    Abstract: Systems, methods, and apparatus for performing the flushing of a plurality of cache lines and/or the invalidation of a plurality of translation look-aside buffer (TLB) entries is described. In one such method, for flushing a plurality of cache lines of a processor a single instruction including a first field that indicates that the plurality of cache lines of the processor are to be flushed and in response to the single instruction, flushing the plurality of cache lines of the processor.
    Type: Application
    Filed: December 22, 2009
    Publication date: June 23, 2011
    Inventors: Martin G. Dixon, Scott D. Rodgers
  • Patent number: 7966476
    Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: June 21, 2011
    Assignee: Intel Corporation
    Inventors: James S. Coke, Peter J. Ruscito, Masood Tahir, David B. Jackson, Ves A. Naydenov, Scott D. Rodgers, Bret L. Toll, Frank Binns
  • Patent number: 7917734
    Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: March 29, 2011
    Assignee: Intel Corporation
    Inventors: James S. Coke, Peter J. Ruscito, Masood Tahir, David B. Jackson, Ves A. Naydenov, Scott D. Rodgers, Bret L. Toll, Frank Binns
  • Publication number: 20080148019
    Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
    Type: Application
    Filed: February 28, 2008
    Publication date: June 19, 2008
    Inventors: James S. Coke, Peter J. Ruscito, Masood Tahir, David B. Jackson, Ves A. Naydenov, Scott D. Rodgers, Bret L. Toll, Frank Binns