Patents by Inventor Scott D. Rodgers

Scott D. Rodgers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080091917
    Abstract: In an embodiment, memory access requests for information stored within a system memory pass through an integrated circuit. The system memory may include a micro-architectural memory region to store instructions and/or data, where the micro-architectural memory region is to be exclusively accessible by a micro-architectural agent The integrated circuit may include memory access director to direct memory access requests to the micro-architectural memory region if the memory access director determines that the memory access request includes a location within the at least one micro-architectural memory region and the micro-architectural agent is operating in a micro-architectural memory region access mode.
    Type: Application
    Filed: October 11, 2006
    Publication date: April 17, 2008
    Inventors: Martin G. Dixon, Scott D. Rodgers, James P. Held, Bill Alexander, Larry O. Smith, Scott H. Robinson, Sham M. Datta
  • Publication number: 20040268090
    Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
    Type: Application
    Filed: June 30, 2003
    Publication date: December 30, 2004
    Inventors: James S. Coke, Peter J. Ruscito, Masood Tahir, David B. Jackson, Ves A. Naydenov, Scott D. Rodgers, Bret L. Toll, Frank Binns
  • Patent number: 5749084
    Abstract: A processor having an address generation unit (AGU) for generating an address corresponding to an entry that is to be fetched. The AGU includes a segment register file for storing address segments, and a circuit for rearranging noncontiguous base and limit bit positions of a first address segment in order to generate a second address segment having all base and limit bits in a contiguous order. The AGU further includes a circuit for executing a single microinstruction to perform read and write operations on a selected field of the second address segments stored in the segment register file.
    Type: Grant
    Filed: April 17, 1996
    Date of Patent: May 5, 1998
    Assignee: Intel Corporation
    Inventors: Kamla P. Huck, Scott D. Rodgers, Andrew F. Glew
  • Patent number: 5636374
    Abstract: In a microprocessor, an apparatus and method for performing memory functions and issuing bus cycles. Special microinstructions are stored in microcode ROM. These microinstructions are used to perform the memory functions and to generate the special bus cycles. Initially, an address corresponding to a requested operation to be performed is generated for one of these special microinstructions. That special microinstruction, along with its address, is then transmitted over the bus to the various units of the microprocessor. When each of the units receives the microinstruction, it determines whether that microinstruction is to be ignored based on the address. If a particular unit ignores the microinstruction, the microinstruction is forwarded to subsequent units in the pipeline for processing. Otherwise, if that particular unit performs the requested operation as specified by the microinstruction's address.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: June 3, 1997
    Assignee: Intel Corporation
    Inventors: Scott D. Rodgers, Keshavan K. Tiruvallur, Michael W. Rhodehamel, Kris G. Konigsfeld, Andrew F. Glew, Haitham Akkary, Milind A. Karnik, James A. Brayton
  • Patent number: 5625788
    Abstract: An out-of-order microprocessor signals event occurrence and provides event handling information utilizing a novel instruction issued to an execution unit upon detection of the condition giving rise to the event. Event information includes the type of event and characteristic information and data for use by a coded routine which handles the event. A reorder buffer stores this information to facilitate event handling actions and state updates. A retirement control circuit of the microprocessor includes a posting mechanism for use by the event handling routine.
    Type: Grant
    Filed: March 1, 1994
    Date of Patent: April 29, 1997
    Assignee: Intel Corporation
    Inventors: Darrell D. Boggs, Scott D. Rodgers
  • Patent number: 5590297
    Abstract: A microprocessor comprising an execution unit for performing arithmetic functions, a fetch unit for determining which entry is to be accessed, an issue unit for accessing the entry from storage in a memory, and an address generation unit for generating an address for that entry. Portions of the base and limit values used for generating the address are stored in separate segments. These separate portions are rearranged so as to form a segment having contiguous base and limit bits. The contiguous base and limit values are then stored in a register file. Copies of the base and limit are stored in control registers and broadcast to other units. Furthermore, a resettable null bit is stored in another register. In addition, the AGU includes a means for selecting a particular field of the register file and performing read/write operations on the selected file.
    Type: Grant
    Filed: January 4, 1994
    Date of Patent: December 31, 1996
    Assignee: Intel Corporation
    Inventors: Kamla P. Huck, Scott D. Rodgers, Andrew F. Glew
  • Patent number: 5577219
    Abstract: A method and apparatus for determining if an effective address for a memory access in a computer processor is above an expand-down memory segment. The apparatus comprises a memory segment limit comparison circuit. The segment limit comparison circuit tests every memory access to determine if the memory access reaches above the top limit of an expand-down memory segment. The comparison circuit consists of an adder that adds an effective address of the memory access to an access.sub.-- size value. The access.sub.-- size value consists of the size of the memory access to be performed minus one in the low order bits and a series of "1" bits in the high order bits necessary to generate a carry if the memory access reaches above the top limit of the expand-down memory segment.
    Type: Grant
    Filed: May 2, 1994
    Date of Patent: November 19, 1996
    Assignee: Intel Corporation
    Inventors: Mark Timko, Scott D. Rodgers
  • Patent number: 5537560
    Abstract: The present invention provides a microinstruction for conditionally selecting one of two data values based upon control states of a processor. The microinstruction is preferably utilized in an out-of-order processor, although it may be used in conventional processors, to perform state dependent operations, including but not limited to privilege or mode sensitive instruction checking, privilege or mode sensitive algorithm execution and processor state updating. This is accomplished through the issuance from microcode to an execution unit upon decoding of a state dependent instruction a conditional move operation that takes advantage of condition resolving circuitry implemented within the execution unit. The execution unit's circuitry makes available processor state information in the form of result values that can be immediately used by the microinstruction upon its execution to resolve the conditions which it specifies.
    Type: Grant
    Filed: March 1, 1994
    Date of Patent: July 16, 1996
    Assignee: Intel Corporation
    Inventors: Darrell D. Boggs, Alan B. Kyker, Scott D. Rodgers
  • Patent number: 5517651
    Abstract: A microprocessor contains an address generation unit, including a segment block, for loading descriptor data and a segment selector in a segment register. Two descriptor loads from a global descriptor table (GDT) and a local descriptor table (LDT) are executed. A 64 bit global descriptor from the GDT is loaded into a temporary register, and a 64 bit local descriptor from the LDT is also loaded into a separate temporary register. If a table indicator bit in the segment selector indicates use of the GDT, then the descriptor data from the GDT is selected. Alternatively, if the table indicator bit in the segment selector indicates the use of the LDT, then the descriptor data from the LDT is selected. The segment block splits the 64 bit descriptor data selected into two 32 bit quantities. The two 32 bit data quantities are input to a test programmable logic array (PLA). The test PLA checks for permission violations, or faults, and detects the need for special handling of the register segment load operation.
    Type: Grant
    Filed: December 29, 1993
    Date of Patent: May 14, 1996
    Assignee: Intel Corporation
    Inventors: Kamla Huck, Andrew F. Glew, Scott D. Rodgers
  • Patent number: 5517657
    Abstract: A mechanism and procedure for providing an efficient pipeline for reading and writing information to a multiple ported segment register file (SRF) in different pipestages. The present invention is operable, in one embodiment, within an address generation unit (AGU) of a processor and is implemented to write the SRF during a particular clock phase of a pipestage and to read to the SRF during another clock phase of another pipestage of the AGU pipeline of a pipelined processor. The read and write of different pipestages associated with separate instructions may occur within a same clock cycle. The write occurs before the read. By reading and writing to the AGU in alternate clock phases, the read and write operations of the SRF do not conflict even though they span different pipestages of the pipeline. Therefore, pipestages of the present invention are not in resource conflict over the SRF read and write operations which occur in a same clock cycle.
    Type: Grant
    Filed: March 30, 1994
    Date of Patent: May 14, 1996
    Assignee: Intel Corporation
    Inventors: Scott D. Rodgers, Kamla P. Huck