Abstract: Methods, systems, and devices for life expectancy monitoring for memory devices are described. A memory device may monitor a parameter of a component of the memory device or the memory device overall, and may determine whether the parameter satisfies a threshold. The parameter may represent or be associated with a lifetime of the component, a level of wear of the component, or an operating parameter violation of the component, or any combination thereof. The memory device may communicate, to a host device, an indication of the parameter satisfying the threshold, and the host device may use the information in the indication to adjust one or more parameters associated with operating the memory device, among other example operations.

Abstract: This disclosure relates to delay line test circuits and methods. In one aspect, an integrated circuit (IC) can include a plurality of delay lines, a selection circuit, a delay comparison circuit, and a control circuit. The plurality of delay lines can generate a plurality of delayed clock signals, and the selection circuit can include a plurality of inputs configured to receive at least the plurality of delayed clock signals. The selection circuit can generate a first output clock signal and a second output clock signal by selecting amongst signals received at the plurality of inputs based on a state of a selection control signal. The delay comparison circuit can compare a delay of the first output clock signal to a delay of the second output clock signal and can generate a delay comparison such as a pass/fail flag based on the result. The control circuit can generate the selection control signal.

Abstract: This disclosure relates to delay line test circuits and methods. In one aspect, an integrated circuit (IC) can include a plurality of delay lines, a selection circuit, a delay comparison circuit, and a control circuit. The plurality of delay lines can generate a plurality of delayed clock signals, and the selection circuit can include a plurality of inputs configured to receive at least the plurality of delayed clock signals. The selection circuit can generate a first output clock signal and a second output clock signal by selecting amongst signals received at the plurality of inputs based on a state of a selection control signal. The delay comparison circuit can compare a delay of the first output clock signal to a delay of the second output clock signal and can generate a delay comparison such as a pass/fail flag based on the result. The control circuit can generate the selection control signal.

Abstract: Disclosed herein are exemplary embodiments of an improved differential input buffer for receiving low power signals and associated methods. The disclosed buffer circuit comprises at least one differential amplifier for receiving as inputs an enable signal (e.g., a clock enable signal) and a reference signal, and provides a differential amplifier output representative of a comparison of the magnitude of the input signals. As improved, input buffer circuitry comprises a pull up stage to pull up the voltage of the differential amplifier output slightly higher during an output low condition. The pull up stage is preferably, but not necessarily, activated only during a problematic condition, such as when both input signals to the differential amplifier are low. By pulling up the output, the input buffer circuit enjoys improved margin, and is able to reliably signal a low power condition even when both inputs are low.

Abstract: A memory device with a low power control circuit that reduces power while ensuring that the device remains in a low power mode until a high power mode has been requested. The low power control circuit initially monitors a control signal using a CMOS buffer or inverter while a reference voltage is grounded or floated. Upon CMOS detection of a signal indicating that a high power mode is required, the low power control circuit monitors the signal using a differential amplifier and the specified reference voltage (i.e., ungrounded and un-floated reference voltage) to determine if the low power mode should be exited. In doing so, the low power control circuit prevents noise from inadvertently causing the device to exit the low power mode while at the same time reduces the power in the device.

Abstract: Disclosed herein are exemplary embodiments of an improved differential input buffer for signal) and a reference signal, and provides a differential amplifier output representative of a comparison of the magnitude of the input signals. As improved, input buffer circuitry comprises a pull up stage to pull up the voltage of the differential amplifier output slightly higher during an output low condition. The pull up stage is preferably, but not necessarily, activated only during a problematic condition, such as when both input signals to the differential amplifier are low. By pulling up the output, the input buffer circuit enjoys improved margin, and is able to reliably signal a low power condition even when both inputs are low.

Abstract: A synchronous mirror delay (SMD) clock recovery and skew adjustment circuit for an integrated circuit is described, having a reduced circuit implementation. The SMD clock recovery and skew adjustment circuit incorporates a delay segment into the forward delay line (FDL) and backward delay line (BDL) that accounts for all or some of the non-variable portion of the asserted clock signal time period. This delay segment allows reduction of the FDL and BDL lines to only those portions necessary to sense and adjust for the portion of the asserted clock signal time period that is variable and that must be adjusted for. The invention allows SMD clock recovery and skew adjustment circuits to be implemented in an optimized manner that exhibits a reduced overall circuit size.

Abstract: An apparatus and associated method are provided to improve the programming of anti-fuse devices in an integrated circuit. A programming circuit capable of programming a plurality of anti-fuse devices in parallel permits a state-changing voltage to be applied to multiple anti-fuses substantially simultaneously using a common control signal.

Abstract: The disclosed embodiments relate to an input buffer circuit. The input buffer circuit comprises a first input buffer having a first operational characteristic and a second input buffer having a second operational characteristic. The output of the first input buffer or the second input buffer is selected responsive to buffer selection input data.

Abstract: A pumped voltage generating circuit for a semiconductor device is disclosed in which measures are taken to minimize undesirable gate-induced diode leakage, especially during standby or idle states of operation of the device. In one embodiment, the pumped voltage generating circuit comprises a charge pump for generating a voltage which is either higher than the voltage of an externally-applied positive supply voltage or lower than the voltage of an externally-applied negative supply voltage. In one disclosed embodiment, a voltage pump generates a pumped voltage and a voltage regulator provides a regulated voltage, where the pumped voltage is characterized as being either more positive than the most positive externally-applied positive voltage supply signal or more negative than the most negative externally-applied negative voltage signal. The pumped voltage and the regulated voltage are applied to respective inputs of a multiplexer receiving a select signal.

Abstract: A sense amplifier circuit includes first and second amplifier circuits. The first amplifier circuit includes a pair of cross-coupled transistors of a first channel type (e.g., N-channel FETs), and the second amplifier circuit includes a pair of cross-coupled transistors of a second channel type (e.g., P-channel FETs). The sense amplifier circuit also includes a third transistor of the second channel type coupled between first nodes of the first and second amplifier circuits, and a fourth transistor of the second channel type coupled between second nodes of the first and second amplifier circuits. The sense amplifier circuit reduces access device leakage of a DRAM cell during LRL refresh access, and improves refresh margin on a DRAM cell with a one written thereto. A method of reducing access device leakage and improving refresh margin using such an improved sense amplifier is also described.

Abstract: A synchronous mirror delay (SMD) clock recovery and skew adjustment circuit for an integrated circuit is described, having a reduced circuit implementation. The SMD clock recovery and skew adjustment circuit incorporates a delay segment into the forward delay line (FDL) and backward delay line (BDL) that accounts for all or some of the non-variable portion of the asserted clock signal time period. This delay segment allows reduction of the FDL and BDL lines to only those portions necessary to sense and adjust for the portion of the asserted clock signal time period that is variable and that must be adjusted for. The invention allows SMD clock recovery and skew adjustment circuits to be implemented in an optimized manner that exhibits a reduced overall circuit size.

Abstract: The disclosed embodiments relate to an input buffer circuit. The input buffer circuit comprises a first input buffer having a first operational characteristic and a second input buffer having a second operational characteristic. The output of the first input buffer or the second input buffer is selected responsive to buffer selection input data.

Abstract: A voltage reference circuit is provided in the periphery of a memory array. Each subarray of the memory array is associated with a respective voltage driver circuit responsible for generating the cell plate and equilibrate reference voltage for the memory cells in the subarray. The voltage reference circuit is connected to and controls each voltage driver so that each driver generates the proper reference voltage. The distributed circuitry substantially reduces the amount of space used within the memory array while mitigating the problems of prior art voltage generator circuits.

Abstract: A pumped voltage generating circuit for a semiconductor device is disclosed in which measures are taken to minimize undesirable gate-induced diode leakage, especially during standby or idle states of operation of the device. In one embodiment, the pumped voltage generating circuit comprises a charge pump for generating a voltage which is either higher than the voltage of an externally-applied positive supply voltage or lower than the voltage of an externally-applied negative supply voltage. In one disclosed embodiment, a voltage pump generates a pumped voltage and a voltage regulator provides a regulated voltage, where the pumped voltage is characterized as being either more positive than the most positive externally-applied positive voltage supply signal or more negative than the most negative externally-applied negative voltage signal. The pumped voltage and the regulated voltage are applied to respective inputs of a multiplexer receiving a select signal.

Abstract: A synchronous mirror delay (SMD) clock recovery and skew adjustment circuit for an integrated circuit is described, having a reduced circuit implementation. The SMD clock recovery and skew adjustment circuit incorporates a delay segment into the forward delay line (FDL) and backward delay line (BDL) that accounts for all or some of the non-variable portion of the asserted clock signal time period. This delay segment allows reduction of the FDL and BDL lines to only those portions necessary to sense and adjust for the portion of the asserted clock signal time period that is variable and that must be adjusted for. The invention allows SMD clock recovery and skew adjustment circuits to be implemented in an optimized manner that exhibits a reduced overall circuit size.

Abstract: A synchronous mirror delay (SMD) clock recovery and skew adjustment circuit for an integrated circuit is described, having a reduced circuit implementation. The SMD clock recovery and skew adjustment circuit incorporates a delay segment into the forward delay line (FDL) and backward delay line (BDL) that accounts for all or some of the non variable portion of the asserted clock signal time period. This delay segment allows reduction of the FDL and BDL lines to only those portions necessary to sense and adjust for the portion of the asserted clock signal time period that is variable and that must be adjusted for. The invention allows SMD clock recovery and skew adjustment circuits to be implemented in an optimized manner that exhibits a reduced overall circuit size.

Abstract: An apparatus and associated method are provided to improve the programming of anti-fuse devices in an integrated circuit. A programming circuit capable of programming a plurality of anti-fuse devices in parallel permits a state-changing voltage to be applied to multiple anti-fuses substantially simultaneously using a common control signal.

Abstract: A synchronous mirror delay (SMD) clock recovery and skew adjustment circuit for an integrated circuit is described, having a reduced circuit implementation. The SMD clock recovery and skew adjustment circuit incorporates a delay segment into the forward delay line (FDL) and backward delay line (BDL) that accounts for all or some of the non-variable portion of the asserted clock signal time period. This delay segment allows reduction of the FDL and BDL lines to only those portions necessary to sense and adjust for the portion of the asserted clock signal time period that is variable and that must be adjusted for. The invention allows SMD clock recovery and skew adjustment circuits to be implemented in an optimized manner that exhibits a reduced overall circuit size.

Abstract: A synchronous mirror delay (SMD) clock recovery and skew adjustment circuit for an integrated circuit is described, having a reduced circuit implementation. The SMD clock recovery and skew adjustment circuit incorporates a delay segment into the forward delay line (FDL) and backward delay line (BDL) that accounts for all or some of the non-variable portion of the asserted clock signal time period. This delay segment allows reduction of the FDL and BDL lines to only those portions necessary to sense and adjust for the portion of the asserted clock signal time period that is variable and that must be adjusted for. The invention allows SMD clock recovery and skew adjustment circuits to be implemented in an optimized manner that exhibits a reduced overall circuit size.