Patents by Inventor Scott Whitney Gould
Scott Whitney Gould has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6832361Abstract: A method and system for analyzing power distribution in an integrated circuit chip includes dividing a clock cycle of the integrated circuit chip into a plurality of time periods, dividing the integrated circuit chip into a plurality of cells, performing a static timing analysis for the plurality of cells to obtain current waveform data for each cell and each time period, and performing a power distribution analysis using the current waveform data.Type: GrantFiled: May 21, 2001Date of Patent: December 14, 2004Assignee: International Business Machines CorporationInventors: John Maxwell Cohn, Scott Whitney Gould, Ronald Dennis Rose, Ivan Wemple, Paul Steven Zuchowski
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Patent number: 6731154Abstract: A method and apparatus for buffering a signal in a voltage island that is in standby or sleep mode. The apparatus uses a buffer(s) that are powered from a global power supply voltage that is always powered, and such buffer(s) are placed within the sleeping island itself. The sleeping island can be at the same or different voltage from the global voltage.Type: GrantFiled: May 1, 2002Date of Patent: May 4, 2004Assignee: International Business Machines CorporationInventors: Thomas Richard Bednar, Scott Whitney Gould, David E. Lackey, Douglas Willard Stout, Paul Steven Zuchowski
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Publication number: 20030206051Abstract: A method and apparatus for buffering a signal in a voltage island that is in standby or sleep mode. The apparatus uses a buffer(s) that are powered from a global power supply voltage that is always powered, and such buffer(s) are placed within the sleeping island itself. The sleeping island can be at the same or different voltage from the global voltage.Type: ApplicationFiled: May 1, 2002Publication date: November 6, 2003Applicant: International Business Machines CorporationInventors: Thomas Richard Bednar, Scott Whitney Gould, David E. Lackey, Douglas Willard Stout, Paul Steven Zuchowski
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Publication number: 20020174409Abstract: A method and system for analyzing power distribution in an integrated circuit chip includes dividing a clock cycle of the integrated circuit chip into a plurality of time periods, dividing the integrated circuit chip into a plurality of cells, performing a static timing analysis for the plurality of cells to obtain current waveform data for each cell and each time period, and performing a power distribution analysis using the current waveform data.Type: ApplicationFiled: May 21, 2001Publication date: November 21, 2002Applicant: International Business Machines CorporationInventors: John Maxwell Cohn, Scott Whitney Gould, Ronald Dennis Rose, Ivan Wemple, Paul Steven Zuchowski
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Patent number: 6345362Abstract: An integrated circuit includes a CPU, a power management unit and plural functional units each dedicated to executing different functions. The power management unit controls the threshold voltage of the different functional units to optimize power/performance operation of the circuit and intelligent power management control responds to the instruction stream and decodes each instruction in turn. This information identifies which of the functional units are required for the particular instruction and by comparing that information to power status, the intelligent power control determines whether the functional units required to execute the command are at the optimum power level. If they are, the command is allowed to proceed, otherwise the intelligent power control either stalls the instruction sequence or modifies process speed.Type: GrantFiled: April 6, 1999Date of Patent: February 5, 2002Assignee: International Business Machines CorporationInventors: Claude Louis Bertin, Alvar Antonio Dean, Kenneth Joseph Goodnow, Scott Whitney Gould, Wilbur David Pricer, William Robert Tonti, Sebastian Theodore Ventrone
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Patent number: 6233191Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: February 22, 2000Date of Patent: May 15, 2001Assignee: International Business Machines CorporationInventors: Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III
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Patent number: 6130854Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 12, 1998Date of Patent: October 10, 2000Assignee: International Business Machines CorporationInventors: Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Terrance John Zittritsch
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Patent number: 6118707Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 10, 1998Date of Patent: September 12, 2000Assignee: International Business Machines CorporationInventors: Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Terrance John Zittritsch
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Patent number: 6075745Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 12, 1998Date of Patent: June 13, 2000Assignee: International Business Machines CorporationInventors: Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Victor Paul Seidel, Terrance John Zittritsch
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Patent number: 6023421Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 12, 1998Date of Patent: February 8, 2000Assignee: International Business Machines CorporationInventors: Kim P. N. Clinton, Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Ralph David Kilmoyer, Michael Joseph Laramie, Victor Paul Seidel, Terrance John Zittritsch
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Patent number: 6021513Abstract: A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.Type: GrantFiled: October 28, 1998Date of Patent: February 1, 2000Assignee: International Business Machines CorporationInventors: Wayne Kevin Beebe, Sally Botala, Scott Whitney Gould, Frank Ray Keyser, III, Wendell Ray Larsen, Ronald Raymond Palmer, Brian Worth
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Patent number: 5949719Abstract: A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.Type: GrantFiled: November 12, 1998Date of Patent: September 7, 1999Assignee: International Business Machines CorporationInventors: Kim P. N. Clinton, Scott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Ralph David Kilmoyer, Michael Joseph Laramie, Victor Paul Seidel, Terrance John Zittritsch
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Patent number: 5910733Abstract: A method and system for defining, placing and routing kernels for a family of integrated circuits is provided. The integrated circuits are defined using repeatable row and column circuit types. Kernels are defined by the intersections of the row and column circuit types in the array. The kernels are placed and routed automatically for each member of the family of integrated circuit arrays, each member being generally characterized by a different size, i.e., a different number of repeatable row or column circuit types.Type: GrantFiled: November 12, 1997Date of Patent: June 8, 1999Assignee: International Business Machines CorporationInventors: Allan Robert Bertolet, Kim P.N. Clinton, Scott Whitney Gould, Frank Ray Keyser III, Timothy Shawn Reny, Terrance John Zittritsch
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Patent number: 5867507Abstract: A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.Type: GrantFiled: December 12, 1995Date of Patent: February 2, 1999Assignee: International Business Machines CorporationInventors: Wayne Kevin Beebe, Sally Botala, Scott Whitney Gould, Frank Ray Keyser III, Wendell Ray Larsen, Ronald Raymond Palmer, Brian Worth
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Patent number: 5781032Abstract: A programmable logic cell has four cell input nodes and a plurality of combinational logic circuits. Four inverter circuits are provided for programmably inverting respective input logic signals, each inverter circuit having an inverter input node connected to a respective cell input node for accepting its respective input logic signal therefrom. Each inverter is programmable into a first state wherein a logic signal representing the complement of the input logic signal is provided to the inverter output node, and a second state wherein a logic signal representing the non-complement of the input logic signal is provided to the inverter output node. The inverter circuits buffer their input logic signals in both their first and second states.Type: GrantFiled: September 9, 1996Date of Patent: July 14, 1998Assignee: International Business Machines CorporationInventors: Allan Robert Bertolet, Kim P.N. Clinton, Christine Marie Fuller, Scott Whitney Gould, Steven Paul Hartman, Joseph Andrew Iadanza, Frank Ray Keyser, Eric Ernest Millham, Timothy Shawn Reny, Brian A. Worth, Gulson Yasar, Terrance John Zittritsch
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Patent number: 5760611Abstract: A programmable logic circuit provides a variety of logic functions including AND/NAND, OR/NOR, XOR/XNOR. Selection of logic function is provided by controlling inputs, using programmable inverters and programmable multiplexers. The logic circuit can be incorporated into a field programmable gate array.Type: GrantFiled: October 25, 1996Date of Patent: June 2, 1998Assignee: International Business Machines CorporationInventor: Scott Whitney Gould
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Patent number: 5761078Abstract: A computer implemented method for the automated placement and routing in the design of field programmable gate arrays achieves optimal timing. In a library of primitives and macros from which a designer may choose to implement a given circuit design, at least some of said macros are "semi-hard" macros where direct connections and relative placements are specified while local bus routing is requested in a manner that does not restrict macro placement. A logical netlist containing references to macros and how to connect them together to perform a logical function is first created. The logical netlist is then translated to a physical netlist using a mapper function. This physical netlist for the semi-hard macros specifies what is to be connected but not how. The best place to put each macro on the field programmable gate array is found using a placer function. The placer function thus determines an absolute position of the macros. Pre-defined macro direct connections are routed using a router function.Type: GrantFiled: March 21, 1996Date of Patent: June 2, 1998Assignee: International Business Machines CorporationInventors: Christine Marie Fuller, Scott Whitney Gould, Steven Paul Hartman, Eric Ernest Millham, Gulsun Yasar
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Patent number: 5748009Abstract: A programmable logic cell has four logic gates, two of which are configurable. The two configurable logic gates are positioned near the logic cell inputs. Each configurable logic gate has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates receive the outputs of the configurable logic gates. Four independent logic cell input nodes are provided, each having associated therewith a programmable input multiplexer. Each input multiplexer can have inputs connected to at least two types of interconnect conductors. The cell also has two output paths, each having associated therewith an independently-controlled output multiplexer. The output of each output multiplexer is connected to an input of the other output multiplexer. Additional features include a multiplexer having inputs connected to two cell input nodes, a select input connected to a third logic cell input node, and an output connected to a cell output node; a system low-skew data (e.g.Type: GrantFiled: September 9, 1996Date of Patent: May 5, 1998Assignee: International Business Machines CorporationInventors: Allan Robert Bertolet, Kim P. N. Clinton, Christine Marie Fuller, Scott Whitney Gould, Steven Paul Hartman, Joseph Andrew Iadanza, Frank Ray Keyser, Eric Ernest Millham, Timothy Shawn Reny, Brian A. Worth, Gulson Yasar, Terrance John Zittritsch
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Patent number: 5745734Abstract: A generalized data decompression engine is incorporated within a field programmable gate array ("FPGA"). The generalized data decompression engine uses a general purpose data decompression technique such as, for example, a Lempel-Ziv type technique. During operation, a compressed configuration bit stream is received by the generalized data decompression engine in the FPGA and is decompressed thereby. A resultant decompressed configuration bit stream is then used to program logic cells within the FPGA.Type: GrantFiled: September 29, 1995Date of Patent: April 28, 1998Assignee: International Business Machines CorporationInventors: David John Craft, Scott Whitney Gould, Frank Ray Keyser, III, Brian Worth
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Patent number: 5734582Abstract: A method and system for defining, placing and routing kernels for a family of integrated circuits is provided. The integrated circuits are defined using repeatable row and column circuit types. Kernels are defined by the intersections of the row and column circuit types in the array. The kernels are placed and routed automatically for each member of the family of integrated circuit arrays, each member being generally characterized by a different size, i.e., a different number of repeatable row or column circuit types.Type: GrantFiled: December 12, 1995Date of Patent: March 31, 1998Assignee: International Business Machines CorporationInventors: Allan Robert Bertolet, Kim P. N. Clinton, Scott Whitney Gould, Frank Ray Keyser, III, Timothy Shawn Reny, Terrance John Zittritsch