Abstract: A package comprising an acoustic device, a polymer frame coupled to the acoustic device, a plurality of frame interconnects located in the polymer frame, where the plurality of frame interconnects are coupled to the acoustic device, a polymer cap layer coupled to the acoustic device though the polymer frame, where the polymer cap layer is configured as a cap for the acoustic device, a plurality of cap interconnects located in the polymer cap layer, where the plurality of cap interconnects are coupled to the plurality of frame interconnects, and a cavity located between the acoustic device and the polymer cap layer. The acoustic device includes a substrate and an acoustic element coupled to the substrate.

Abstract: A package that includes an acoustic device, a frame coupled to the acoustic device and a cap substrate coupled to the acoustic device through the frame. The acoustic device includes a substrate and an acoustic element coupled to the substrate. The cap substrate includes an inductor. The cap substrate is configured as a cap for the acoustic device. The package includes a cavity located between the acoustic device and the cap substrate. The frame may include a polymer frame.

Abstract: A package that includes an integrated device, a substrate coupled to the integrated device, and an encapsulation layer coupled to the substrate. The encapsulation layer encapsulates the integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects located in the at least one dielectric layer, wherein at least one of the interconnects has a rectangular side cross-section having at least one corner with a corner radius less than a corner radius threshold.

Abstract: A package that includes an integrated device, a substrate coupled to the integrated device, and an encapsulation layer coupled to the substrate. The encapsulation layer encapsulates the integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects located in the at least one dielectric layer, wherein at least one of the interconnects has a rectangular side cross-section having at least one corner with a corner radius less than a corner radius threshold.

Abstract: A mechanically stable main body having a cutout, into which an ESD protection element is at least partly embedded and mechanically fixed by means of a connection means. Electrical terminals of the protection element are connected to terminal pads on the top side of the main body by way of a structured metallic layer bearing on main body and protection element.

Abstract: A package that includes an integrated device, a substrate coupled to the integrated device, and an encapsulation layer coupled to the substrate. The encapsulation layer encapsulates the integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects located in the at least one dielectric layer, a buffer dielectric layer coupled to the at least one dielectric layer, and a buffer interconnect located at least in the buffer dielectric layer.

Abstract: A package that includes an integrated device, a substrate coupled to the integrated device, and an encapsulation layer coupled to the substrate. The encapsulation layer encapsulates the integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects located in the at least one dielectric layer, a buffer dielectric layer coupled to the at least one dielectric layer, and a buffer interconnect located at least in the buffer dielectric layer.

Abstract: A multi-LED system is disclosed. In an embodiment a multi-LED system includes a ceramic multilayer substrate in which at least two ESD protection structures are integrated, at least two light-emitting diodes arranged on the substrate and at least two capping layers covering one of the light-emitting diodes.

Abstract: A green film composed of varistor material laminated on a ceramic main body, which is provided with metallizations on both sides, and is sintered to form a varistor layer. A terminating electrode pair completes the arrangement and allows the varistor layer to be operated as a varistor. The upper second electrode pair can serve directly as a terminal contact for mounting an electrical component.

Abstract: A component assembly is disclosed. In an embodiment the assembly includes a carrier, a metallic structure arranged on the carrier, wherein the metallic structure comprises at least one cavity and an electrical component arranged at least in part in the cavity, wherein the metallic structure comprises at least two part regions which are not connected to each other by any further part of the metallic structure, and wherein the cavity is located between the two part regions. The assembly further includes two contact areas located on the carrier, wherein the component is located on the two contact areas such that each part region of the two part regions is located on one of the two contact areas.

Abstract: A multi-LED system is disclosed. In an embodiment a multi-LED system includes a ceramic multilayer substrate in which at least two ESD protection structures are integrated, at least two light-emitting diodes arranged on the substrate and at least two capping layers covering one of the light-emitting diodes.

Abstract: A green film composed of varistor material is laminated on a ceramic main body (GK), which is provided with metallizations (EP1, AF) on both sides, and is sintered to form a varistor layer (VS). A terminating electrode pair (EP1, EP2) completes the arrangement and allows the varistor layer to be operated as a varistor. The upper second electrode pair (EP2) can serve directly as a terminal contact for mounting an electrical component.

Abstract: A mechanically stable main body having a cutout, into which an ESD protection element is at least partly embedded and mechanically fixed by means of a connection means. Electrical terminals of the protection element are connected to terminal pads on the top side of the main body by way of a structured metallic layer bearing on main body and protection element.

Abstract: A carrier plate includes a substrate and at least one conductor track. The conductor track includes a first layer, which is applied directly on the substrate, and a second layer, which is arranged on the first layer. The second layer includes a supply line region and a soldering region. Furthermore, the second layer is completely interrupted between the supply line region and the soldering region. A device can be produced with a carrier plate and an electrical component arranged on the carrier plate.

Abstract: A method for producing an electric contact-connection of a multilayer component is disclosed. In an embodiment, the method includes providing a main body of the multilayer component having internal electrode layers, applying an electrically conductive material and applying a photosensitive material on the electrically conductive material. The method further includes structuring the electrically conductive material via the photosensitive material such that the internal electrode layers alternatingly are covered and uncovered by the electrically conductive material and applying an insulating material after structuring the electrically conductive material such that the internal electrode layers are alternatingly covered by the electrically conductive material and by the insulating material.

Abstract: A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.

Abstract: A method for producing a multilayer substrate (1) is specified, wherein a main body (26) comprising a plurality of ceramic layers (2) is provided, wherein at least one layer (2) comprises a hole (27). In order to form a plated-through hole (4, 18, 20, 21), the hole (27) is filled with a metal by depositing the metal from a solution. Furthermore, a multilayer substrate is specified wherein a plated-through hole (4, 18, 20, 21) in the interior of the main body (26) is connected to a further contact (11), wherein the plated-through hole (4, 18, 20, 21) comprises a different material than the further contact (11) and/or is produced by a different method.

Abstract: A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.

Abstract: A light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip is arranged in a manner at least partly recessed in the at least one cavity, and an ESD protection element, which is formed by a partial region of the carrier. Furthermore, a light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip arranged on the carrier, and an electrical component arranged at least partly recessed in the at least one cavity. Furthermore, the light-emitting diode device includes an ESD protection element, which is formed by a partial region of the carrier.

Abstract: A light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip is arranged in a manner at least partly recessed in the at least one cavity, and an ESD protection element, which is formed by a partial region of the carrier. Furthermore, a light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip arranged on the carrier, and an electrical component arranged at least partly recessed in the at least one cavity. Furthermore, the light-emitting diode device includes an ESD protection element, which is formed by a partial region of the carrier.