Patents by Inventor Sebastian T. Ventrone

Sebastian T. Ventrone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190214348
    Abstract: Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 11, 2019
    Inventors: Wen Liu, Sebastian T. Ventrone, Adam C. Smith, Janice M. Adams, Nazmul Habib
  • Patent number: 10249590
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to stacked dies using one or more interposers and methods of manufacture. The structure includes: at least one die comprising a plurality of via interconnects, the plurality of via interconnects comprising at least one functional via interconnect, one defective via interconnect and one redundant functional via interconnect to compensate for the one defective via interconnect; and an interposer which includes interconnects that aligns to and electrically connects the at least one functional via interconnect and the redundant functional via interconnect of different dies when the interposer is oriented in a predetermined orientation.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: April 2, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sudeep Mandal, Sebastian T. Ventrone, Richard S. Graf
  • Publication number: 20180350684
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to stacked dies using one or more interposers and methods of manufacture. The structure includes: at least one die comprising a plurality of via interconnects, the plurality of via interconnects comprising at least one functional via interconnect, one defective via interconnect and one redundant functional via interconnect to compensate for the one defective via interconnect; and an interposer which includes interconnects that aligns to and electrically connects the at least one functional via interconnect and the redundant functional via interconnect of different dies when the interposer is oriented in a predetermined orientation.
    Type: Application
    Filed: June 6, 2017
    Publication date: December 6, 2018
    Inventors: SUDEEP MANDAL, SEBASTIAN T. VENTRONE, RICHARD S. GRAF
  • Patent number: 10083891
    Abstract: An IC chip package includes: a base substrate; an interposer substrate including a plurality of wires therein, the interposer substrate operatively coupled to the base substrate; and a processor operatively positioned on the interposer substrate. A memory is operatively positioned on the interposer substrate and operatively coupled to the processor through the interposer substrate. The memory includes: a 3D DRAM stack, a thermoelectric heat pump coupled directly to an uppermost layer of the 3D DRAM stack, and a memory controller operatively coupled to the 3D DRAM stack to control operation of the 3D DRAM stack. A temperature controller operatively coupled to the thermoelectric heat pump controls a temperature of the 3D DRAM stack using the thermoelectric heat pump. A lid may thermally couple to an uppermost surface of the processor and an uppermost surface of the thermoelectric heat pump.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: September 25, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Richard S. Graf, Sebastian T. Ventrone, Ezra D. B. Hall
  • Patent number: 9972606
    Abstract: A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Richard S. Graf, Sebastian T. Ventrone
  • Publication number: 20180019227
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to intelligent through silicon via sharing in 3D-IC integrated structures and methods of manufacture. The structure includes: a plurality of stacked dies each containing at least one macro device; and a layer structure positioned between the plurality of stacked dies which comprises a control structured to route signals between the at least one macro device of a first stacked die and the at least one macro device of a second stacked die of the plurality of stacked dies.
    Type: Application
    Filed: July 14, 2016
    Publication date: January 18, 2018
    Inventors: Sebastian T. Ventrone, Sudeep Mandal
  • Patent number: 9871020
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to intelligent through silicon via sharing in 3D-IC integrated structures and methods of manufacture. The structure includes: a plurality of stacked dies each containing at least one macro device; and a layer structure positioned between the plurality of stacked dies which comprises a control structured to route signals between the at least one macro device of a first stacked die and the at least one macro device of a second stacked die of the plurality of stacked dies.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: January 16, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sebastian T. Ventrone, Sudeep Mandal
  • Publication number: 20170373024
    Abstract: Chip packages with improved tamper resistance and methods of using such chip packages to provide improved tamper resistance. A lead frame includes a die attach paddle, a plurality of outer lead fingers, and a plurality of inner lead fingers located between the outer lead fingers and the die attach paddle. A chip is attached to the die attach paddle. The chip includes a surface having an outer boundary and a plurality of bond pads arranged proximate to the outer boundary. A first plurality of wires extend from the outer lead fingers to respective locations on the surface of the chip that are interior of the outer boundary relative to the bond pads. A tamper detection circuit is coupled with the first plurality of wires. A second plurality of wires extend from the inner lead fingers to the bond pads on the chip. The second plurality of wires are located between the lead frame and the first plurality of wires.
    Type: Application
    Filed: June 28, 2016
    Publication date: December 28, 2017
    Inventors: Richard S. Graf, Ezra D.B. Hall, Faraydon Pakbaz, Sebastian T. Ventrone
  • Publication number: 20170271309
    Abstract: A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.
    Type: Application
    Filed: May 25, 2017
    Publication date: September 21, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Richard S. Graf, Sebastian T. Ventrone
  • Publication number: 20170255471
    Abstract: Various embodiments include processors for processing operations. In some cases, a processor includes: an instruction fetch component configured to fetch processing instructions; an instruction cache component connected with the instruction fetch component, configured to store the processing instructions; an execution component connected with the instruction cache component, configured to execute the processing instructions; a monitor component connected with the execution component, configured to receive execution results from the processing instructions; and a content addressable memory (CAM) component connected with the instruction fetch component and the monitor component, wherein the monitor component stores a portion of the execution results in the CAM for subsequent use in bypassing the execution component.
    Type: Application
    Filed: March 7, 2016
    Publication date: September 7, 2017
    Inventors: Jack R. Smith, Sebastian T. Ventrone, Ezra D. B. Hall
  • Patent number: 9741695
    Abstract: A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: August 22, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Richard S. Graf, Sebastian T. Ventrone
  • Publication number: 20170200698
    Abstract: A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.
    Type: Application
    Filed: January 13, 2016
    Publication date: July 13, 2017
    Applicant: Global Foundries Inc.
    Inventors: Richard S. Graf, Sebastian T. Ventrone
  • Patent number: 9606291
    Abstract: Integrated optical structures include a first wafer layer, a first insulator layer directly connected to the top of the first wafer layer, a second wafer layer directly connected to the top of the first insulator layer, a second insulator layer directly connected to the top of the second wafer layer, and a third wafer layer directly connected to the top of the second insulator layer. Such structures include: a first optical waveguide positioned within the second wafer layer; an optical coupler positioned within the second wafer layer, the second insulator layer, and the third wafer layer; and a second optical waveguide positioned within the third wafer layer. The optical coupler transmits an optical beam from the first optical waveguide to the second optical waveguide through the second insulator layer.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: March 28, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John J. Ellis-Monaghan, Brendan S. Harris, Vibhor Jain, Yves T. Ngu, Sebastian T. Ventrone
  • Patent number: 9600901
    Abstract: Various embodiments include solutions for analyzing three-dimensional video data. Various embodiments include a system having: at least one sensor for detecting at least one of object occlusion or drift in visual data; and a digital signal processor coupled with the at least one sensor, the digital signal processor having at least one database (DB) including target template sets for analyzing both object occlusion in visual data and drift in visual data, wherein the digital signal processor is configured to switch between one of the target template sets and a distinct target template set in the at least one DB based upon detection of the at least one of object occlusion or drift in the visual data.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: March 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Ezra D. B. Hall, Aydin Suren, Clark N. Vandam, Sebastian T. Ventrone
  • Patent number: 9588293
    Abstract: Various particular embodiments include a primary waveguide including an end section; cantilevered waveguides, each cantilevered waveguide including an end section disposed adjacent the end section of the primary waveguide; and control pins for applying an electrical bias to the cantilevered waveguides to selectively displace the end sections of the cantilevered waveguides away from the end section of the primary waveguide.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: March 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: John J. Ellis-Monaghan, Brendan S. Harris, Vibhor Jain, Thomas Kessler, Yves T. Ngu, Sebastian T. Ventrone
  • Publication number: 20160377805
    Abstract: Various particular embodiments include a primary waveguide including an end section; cantilevered waveguides, each cantilevered waveguide including an end section disposed adjacent the end section of the primary waveguide; and control pins for applying an electrical bias to the cantilevered waveguides to selectively displace the end sections of the cantilevered waveguides away from the end section of the primary waveguide.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Inventors: John J. Ellis-Monaghan, Brendan S. Harris, Vibhor Jain, Thomas Kessler, Yves T. Ngu, Sebastian T. Ventrone
  • Publication number: 20160377806
    Abstract: Integrated optical structures include a first wafer layer, a first insulator layer directly connected to the top of the first wafer layer, a second wafer layer directly connected to the top of the first insulator layer, a second insulator layer directly connected to the top of the second wafer layer, and a third wafer layer directly connected to the top of the second insulator layer. Such structures include: a first optical waveguide positioned within the second wafer layer; an optical coupler positioned within the second wafer layer, the second insulator layer, and the third wafer layer; and a second optical waveguide positioned within the third wafer layer. The optical coupler transmits an optical beam from the first optical waveguide to the second optical waveguide through the second insulator layer.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Inventors: John J. Ellis-Monaghan, Brendan S. Harris, Vibhor Jain, Yves T. Ngu, Sebastian T. Ventrone
  • Patent number: 9496981
    Abstract: A system is provided for securing information residing on a circuit (e.g., processor). In particular, a system and method is provided for masking electromagnetic interference (EMI) emissions emitting from a circuit using a random noise generator in combination with a low noise amplifier and antenna. The random number generator matches a frequency of a circuit to be protected, and generates a random signal to be superimposed on data. The low noise amplifier receives the random signal from the random number generator, and an antenna receives the random signal from the low noise amplifier and transmits the random signal to mask the data of the circuit to be protected.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: November 15, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kerry Bernstein, Sebastian T. Ventrone
  • Patent number: 9472483
    Abstract: A chip fabricated from a semiconductor material is disclosed, which may include active devices located below a first depth from the chip back side, and a structure to remove heat from the active devices to the chip back side. The structure may include thermally conductive partial vias (TCPVs), which may include a recess with a depth, from the chip back side towards the active devices less than the first depth. Each TCPV may include a barrier layer deposited within the recess and deposited upon the back side of the chip. Each TCPV may also include a thermally conductive layer deposited upon the barrier layer. The structure may also include through-silicon vias (TSVs) electrically connected to active devices, extending from the back side to an active device side of the chip to conductively remove heat from the active devices to the back side of the chip.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: October 18, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Richard S. Graf, Sudeep Mandal, Sebastian T. Ventrone
  • Patent number: 9412736
    Abstract: In an approach to fabricating a silicon on insulator wafer, one or more semiconductor device elements are implanted and one or more shallow trench isolations are formed on a top surface of a first semiconductor wafer. A first dielectric material layer is deposited over the top surface of the first semiconductor wafer, filling the shallow trench isolations. A dielectric material layer on a bottom surface of a second semiconductor wafer is bonded to a dielectric material layer on the top of the first semiconductor wafer and one or more semiconductor devices are formed on a top surface of the second semiconductor wafer. Then, one or more through silicon vias are created connecting the one or more semiconductor devices on the top surface of the second semiconductor wafer and the one or more semiconductor device elements on the top surface of the first semiconductor wafer.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: August 9, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yan Ding, Vibhor Jain, Thomas Kessler, Yves T. Ngu, Robert M. Rassel, Sebastian T. Ventrone