Patents by Inventor See Taur Lee

See Taur Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7834686
    Abstract: Methods to implement power control in a digital power amplifier are described.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: November 16, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Robert Bogdan Staszewski, See Taur Lee, Dirk Leipold
  • Publication number: 20100271131
    Abstract: Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high power and high efficiency radio frequency power amplifier to be realized using multiple low voltage CMOS transistors or micro power amplifiers. The power combiner may be printed on a package substrate and realized either using single layer substrate through edge coupling or multiple layers substrate through broadside coupling. The micro power amplifiers may be fabricated using low voltage CMOS technology and electrical connections between the outputs from the micro power amplifiers and the power combiner may be provided through stud bumps in a flip chip technology. With the tunable matching circuits, the present invention allows the narrow band power combiner to be tuned to different frequencies.
    Type: Application
    Filed: July 6, 2010
    Publication date: October 28, 2010
    Applicant: Texas Instruments Incorporated
    Inventors: Robert Bogdan Staszewski, See Taur Lee
  • Patent number: 7777572
    Abstract: Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high power and high efficiency radio frequency power amplifier to be realized using multiple low voltage CMOS transistors or micro power amplifiers. The power combiner may be printed on a package substrate and realized either using single layer substrate through edge coupling or multiple layers substrate through broadside coupling. The micro power amplifiers may be fabricated using low voltage CMOS technology and electrical connections between the outputs from the micro power amplifiers and the power combiner may be provided through stud bumps in a flip chip technology. With the tunable matching circuits, the present invention allows the narrow band power combiner to be tuned to different frequencies.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: August 17, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Robert Bogdan Staszewski, See Taur Lee
  • Publication number: 20100007423
    Abstract: Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high power and high efficiency radio frequency power amplifier to be realized using multiple low voltage CMOS transistors or micro power amplifiers. The power combiner may be printed on a package substrate and realized either using single layer substrate through edge coupling or multiple layers substrate through broadside coupling. The micro power amplifiers may be fabricated using low voltage CMOS technology and electrical connections between the outputs from the micro power amplifiers and the power combiner may be provided through stud bumps in a flip chip technology. With the tunable matching circuits, the present invention allows the narrow band power combiner to be tuned to different frequencies.
    Type: Application
    Filed: September 21, 2009
    Publication date: January 14, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Robert Bogdan Staszewski, See Taur Lee
  • Patent number: 7612612
    Abstract: Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high power and high efficiency radio frequency power amplifier to be realized using multiple low voltage CMOS transistors or micro power amplifiers. The power combiner may be printed on a package substrate and realized either using single layer substrate through edge coupling or multiple layers substrate through broadside coupling. The micro power amplifiers may be fabricated using low voltage CMOS technology and electrical connections between the outputs from the micro power amplifiers and the power combiner may be provided through stud bumps in a flip chip technology. With the tunable matching circuits, the present invention allows the narrow band power combiner to be tuned to different frequencies.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: November 3, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Robert Bogdan Staszewski, See Taur Lee
  • Publication number: 20090096525
    Abstract: Methods to implement power control in a digital power amplifier are described.
    Type: Application
    Filed: June 6, 2008
    Publication date: April 16, 2009
    Applicant: Texas Instruments
    Inventors: Robert Bogdan Staszewski, See Taur Lee, Dirk Leipold
  • Publication number: 20080315954
    Abstract: Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high power and high efficiency radio frequency power amplifier to be realized using multiple low voltage CMOS transistors or micro power amplifiers. The power combiner may be printed on a package substrate and realized either using single layer substrate through edge coupling or multiple layers substrate through broadside coupling. The micro power amplifiers may be fabricated using low voltage CMOS technology and electrical connections between the outputs from the micro power amplifiers and the power combiner may be provided through stud bumps in a flip chip technology. With the tunable matching circuits, the present invention allows the narrow band power combiner to be tuned to different frequencies.
    Type: Application
    Filed: September 24, 2007
    Publication date: December 25, 2008
    Applicant: Texas Instruments
    Inventors: Robert Bogdan Staszewski, See Taur Lee
  • Patent number: 7453142
    Abstract: A transformer system includes a package substrate having a surface. A plurality of electrically conductive pads are arranged in spaced apart relationship relative to each other on the substrate surface. A first winding is defined by a first electrically conductive path between a first input and a first output, the first electrically conductive path including at least one wire connected between at least one first pad pair of the electrically conductive pads. At least one electrically conductive pad of each first pad pair is at the substrate surface. A second winding is defined by a second electrically conductive path between a second input and a second output, the second electrically conductive path including at least one wire connected between at least one second pad pair of the electrically conductive pads. At least one electrically conductive pad of each second pad pair is at the substrate surface.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: November 18, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: See Taur Lee, Solti Peng, Dirk Leipold, James Fred Salzman
  • Patent number: 6985028
    Abstract: Programmable linear-in-dB or linear bias current source with respect to an input voltage is provided. The linear-in-dB or linear bias current may be clipped at a minimum current level, a maximum current level, or a combination thereof. Preferably, the minimum and maximum current levels are determined by the use of one or more constant current sources. The constant current sources limit the amount of voltage applied to the gates of one or more transistors, which in turn control the output current. The use of the circuit may be used to generate linear or reverse-linear current levels with respect to an input voltage. The output of the current generator may be used as an input to a power-amplifier driver, for example.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: January 10, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: See Taur Lee, Abdellatif Bellaouar
  • Publication number: 20040251977
    Abstract: A method of implementing a low-current, area-efficient and flicker noise free bias CMOS voltage control oscillator (VCO) 200 employs a resistor 202 as a current source to the VCO core. By eliminating the transistor current source as employed in conventional designs, the CMOS VCO 200 does not require any reference current source, and thus achieves at least a 10-20% current savings over that achievable using prior art techniques. Further, noise amplification issues from the reference current source do not exist since only a resistor 202 is used as a current source, yielding only resistor thermal noise. The method employed allows low supply pushing, an important factor to be considered in VCO designs.
    Type: Application
    Filed: March 26, 2004
    Publication date: December 16, 2004
    Inventors: Abdellatif Bellaouar, See Taur Lee
  • Publication number: 20040189375
    Abstract: Programmable linear-in-dB or linear bias current source with respect to an input voltage is provided. The linear-in-dB or linear bias current may be clipped at a minimum current level, a maximum current level, or a combination thereof. Preferably, the minimum and maximum current levels are determined by the use of one or more constant current sources. The constant current sources limit the amount of voltage applied to the gates of one or more transistors, which in turn control the output current. The use of the circuit may be used to generate linear or reverse-linear current levels with respect to an input voltage. The output of the current generator may be used as an input to a power-amplifier driver, for example.
    Type: Application
    Filed: October 20, 2003
    Publication date: September 30, 2004
    Inventors: See Taur Lee, Abdellatif Bellaouar
  • Publication number: 20040036541
    Abstract: A wideband digital quadrature local oscillator (LO) generator (300) using clocked-CMOS (C2MOS) latches (302, 304) can operate at very high frequencies, while consuming less current and having lower phase noise as compared to prior art quadrature LO generators using Source-coupled logic (SCL) latches. In addition, the LO generator (300) has no low frequency limit and can output rail-to-rail square waves.
    Type: Application
    Filed: August 26, 2002
    Publication date: February 26, 2004
    Inventors: Sher Jiun Fang, See Taur Lee, Abdellatif Bellaouar