Patents by Inventor Seiichi Iwamatsu

Seiichi Iwamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7306896
    Abstract: An electron beam duplication lithography apparatus and method for focusing electrons emitted from a mask plate as a result of an application of an electric field between a mask plate and a duplication plate. Irradiation of electrons from the mask plate is assisted through an electric field lens or magnetic field lens, or a combination thereof from an electron field emission material formed into a pattern on a flat surface of a substrate. The result is that a congruent or similar pattern is lithographed by electron beam exposure onto an electron beam resist film from a field emission film having the congruent or similar pattern to be created.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: December 11, 2007
    Inventor: Seiichi Iwamatsu
  • Publication number: 20070230767
    Abstract: A method and device for extracting medically effective information by applying a millimeter-wave band electromagnetic wave to an organism and analyzing transmission, reflection and spontaneous radiation signals.
    Type: Application
    Filed: July 11, 2005
    Publication date: October 4, 2007
    Applicant: INTELLECTUAL PROPERTY BANK CORP.
    Inventors: Seiichi Iwamatsu, Tomohiro Marui, Nobuaki Kawaguchi, Makoto Shinozaki
  • Publication number: 20060151719
    Abstract: An electron beam duplication lithography apparatus and method for focusing electrons emitted from a mask plate as a result of an application of an electric field between a mask plate and a duplication plate. Irradiation of electrons from the mask plate is assisted through an electric field lens or magnetic field lens, or a combination thereof from an electron field emission material formed into a pattern on a flat surface of a substrate. The result is that a congruent or similar pattern is lithographed by electron beam exposure onto an electron beam resist film from a field emission film having the congruent or similar pattern to be created.
    Type: Application
    Filed: February 14, 2006
    Publication date: July 13, 2006
    Applicant: SI Diamond Technology, Inc.
    Inventor: Seiichi Iwamatsu
  • Patent number: 7011927
    Abstract: An electron beam duplication lithography apparatus and method for focusing electrons emitted from a mask plate as a result of an application of an electric field between a mask plate and a duplication plate. Irradiation of electrons from the mask plate is assisted through an electric field lens or magnetic field lens, or a combination thereof from an electron field emission material formed into a pattern on a flat surface of a substrate. The result is that a congruent or similar pattern is lithographed by electron beam exposure onto an electron beam resist film from a field emission film having the congruent or similar pattern to be created.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: March 14, 2006
    Assignee: Si Diamond Technology, Inc.
    Inventor: Seiichi Iwamatsu
  • Publication number: 20050121623
    Abstract: An electron beam duplication lithography apparatus and method for focusing electrons emitted from a mask plate as a result of an application of an electric field between a mask plate and a duplication plate. Irradiation of electrons from the mask plate is assisted through an electric field lens or magnetic field lens, or a combination thereof from an electron field emission material formed into a pattern on a flat surface of a substrate. The result is that a congruent or similar pattern is lithographed by electron beam exposure onto an electron beam resist film from a field emission film having the congruent or similar pattern to be created.
    Type: Application
    Filed: January 21, 2005
    Publication date: June 9, 2005
    Applicant: SI Diamond Technology, Inc.
    Inventor: Seiichi Iwamatsu
  • Patent number: 6849856
    Abstract: An electron beam duplication lithography apparatus and method for focusing electrons emitted from a mask plate as a result of an application of an electric field between a mask plate and a duplication plate. Irradiation of electrons from the mask plate is assisted through an electric field lens or magnetic field lens, or a combination thereof from an electron field emission material formed into a pattern on a flat surface of a substrate. The result is that a congruent or similar pattern is lithographed by electron beam exposure onto an electron beam resist film from a field emission film having the congruent or similar pattern to be created.
    Type: Grant
    Filed: April 17, 2001
    Date of Patent: February 1, 2005
    Assignee: SI Diamond Technology, Inc.
    Inventor: Seiichi Iwamatsu
  • Patent number: 5504037
    Abstract: A method for forming optimized film metal interconnects employed in integrated circuit structures have a width, L, and a spatial separation or spacing, S, according to the following characteristics: interconnect width, L.gtoreq.0.1 mm; interconnect spatial separation, S.gtoreq.0.2 .mu.m, interconnect thickness, T.sub.A1 .ltoreq.2L mm; and interlayer insulating film thickness, T.sub.I .ltoreq.2L min. More particularly, the layout is characterized by having the ranges of 0.1.ltoreq.L.ltoreq.0.8 mm and 0.2 mm.ltoreq.S.ltoreq.1 mm. As a result, IC signal switching speed is optimized for IC's designed in the sub-micron integration scale regime.
    Type: Grant
    Filed: July 29, 1993
    Date of Patent: April 2, 1996
    Assignee: Seiko Epson Corporation
    Inventor: Seiichi Iwamatsu
  • Patent number: 5327011
    Abstract: A semiconductor device has an interconnect layer, connected to a connecting region, such as a diffusion region or layer formed on the surface of a substrate, through a contact hole formed in an interlayer insulating film, which includes a concavity, representing a defective portion, extending from the bottom portion of the contact hole to the surface of the interconnect layer. This defective portion occurs because the metal comprising the interconnect layer will not penetrate to completely fill the contact hole. To correct for this formed defective portion, the concavity, the concavity is permitted to be formed followed by its filling with a plug electrode comprising a high quality penetration metal film, such as, tungsten. As a result, the mechanical as well as electrical characteristics of the interconnect layer connection to the connecting region is significantly improve by the presence of the plug electrode.
    Type: Grant
    Filed: July 22, 1992
    Date of Patent: July 5, 1994
    Assignee: Seiko Epson Corporation
    Inventor: Seiichi Iwamatsu
  • Patent number: 5294821
    Abstract: Thin-film SOI semiconductor devices formed in a thin film Si semiconductor substrate layer formed on an insulating layer on a semiconductor substrate have improved electrical characteristics and reliable reproducibility of those characteristics in the mass production, which are obtained by utilizing semiconductor substrate having high concentrations of active impurities, or by utilizing voltage biased, impurity diffusion regions in the surface of the semiconductor substrate aligned beneath CMOS FETs formed in the thin film Si layer. They can also be obtained by extension of the semiconductor substrate through the insulating film to the channel region of the CMOS FETs formed in a thin film Si regions. Further, reliably reproducible contact connection of electrodes to buried thin film Si layers is also achieved.
    Type: Grant
    Filed: October 8, 1991
    Date of Patent: March 15, 1994
    Assignee: Seiko Epson Corporation
    Inventor: Seiichi Iwamatsu
  • Patent number: 5258219
    Abstract: Thin film metal interconnects employed in integrated circuit structures have a width, L, and a spatial separation or spacing, S, according to the following characteristics: interconnect width, L.gtoreq.0.1 .mu.m; interconnect spatial separation, S.gtoreq.0.2 .mu.m, interconnect thickness, T.sub.A1 .ltoreq.2L .mu.m; and interlayer insulating film thickness, T.sub.I .ltoreq.2L .mu.m. More particularly, the layout is characterized by having the ranges of 0.1.ltoreq.L.ltoreq.0.8 .mu.m and 0.2 .mu.m.ltoreq.S.ltoreq.1 .mu.m. As a result, IC signal switching speed is optimized for IC's designed in the submicron integration scale regime.
    Type: Grant
    Filed: June 1, 1992
    Date of Patent: November 2, 1993
    Assignee: Seiko Epson Corporation
    Inventor: Seiichi Iwamatsu
  • Patent number: 5179426
    Abstract: A transistor structure which utilizes the Josephson effect and/or tunneling effect. The Josephson transistors of the invention are composed of superconductive films and tunneling films and work at a high speed with a low energy consumption. They are suitable for the construction of integrated circuits, especially digital circuits.
    Type: Grant
    Filed: August 1, 1988
    Date of Patent: January 12, 1993
    Assignee: Seiko Epson Corporation
    Inventor: Seiichi Iwamatsu
  • Patent number: 5142640
    Abstract: A trench gate MOS FET having one of the following features: a drain diffusion layer and/or a source diffusion layer having a two-layer structure consisting of a high concentration layer and a low concentration layer; at least a drain diffusion layer having a low concentration layer adjacent to the semiconductor surface of a trench gate and a high concentration layer adjacent to the low concentration layer; a gate oxide film formed to have a greater thickness at the overlapping portion of the diffusion layer and the gate electrode than at the other portions thereof; two trench gates provided on the semiconductor surface so as to control the conductivity of a channel region between the trench gates; or a trench isolation region provided on the semiconductor substrate in contact with the trench gate.
    Type: Grant
    Filed: June 2, 1989
    Date of Patent: August 25, 1992
    Assignee: Seiko Epson Corporation
    Inventor: Seiichi Iwamatsu
  • Patent number: 5119170
    Abstract: A method of forming thin film metal interconnects employed in integrated circuit structures comprising the step of laying out the interconnects so that the patterned interconnects have a relationship of interconnect width, L, and interconnect spatial separation, S, so that S>1 .mu.m>L. In particular, line width, L, is equal to or less than 0.8 .mu.m, spatial separation, S, is in the range of 1.0 .mu.m to 1.2 .mu.m and interconnect thickness, T.sub.A1, is about 0.5 .mu.m thereby providing effective optimization in the amount of reduction in interconnect spatial capacitance resulting in increased operation speed of the integrated circuit structure.
    Type: Grant
    Filed: September 9, 1991
    Date of Patent: June 2, 1992
    Assignee: Seiko Epson Corp.
    Inventor: Seiichi Iwamatsu
  • Patent number: 5071832
    Abstract: A field effect type Josephson transistor in which a source electrode and a drain electrode are provided with a gap therebetween, a tunnel film is provided in the gap between the source electrode and drain electrode, and a gate electrode for field-controlling the tunnel current through the tunnel film is provided. The transistor of such structure is suitable for mass-production and is utilized in manufacture of integrated circuits.
    Type: Grant
    Filed: October 19, 1989
    Date of Patent: December 10, 1991
    Assignee: Seiko Epson Corporation
    Inventor: Seiichi Iwamatsu
  • Patent number: 4902897
    Abstract: An ion beam exposure device including an ion beam source and an ion beam mask is provided. The ion beam source is formed from a thin film which is disposed between a vacuum side and a gas side. The film is in the form of a plate having a fine wire buried therein or a crystal boundary formed therein. An electric field supplied to the plate ionizing the gas passing from the gas source side of the plate to the vacuum side. A patterned ion mask may be formed directly on the ion beam source, thereby creating an ion beam gun which emits an ion beam in the desired pattern.
    Type: Grant
    Filed: October 13, 1987
    Date of Patent: February 20, 1990
    Assignee: Seiko Epson Corporation
    Inventor: Seiichi Iwamatsu
  • Patent number: 4576851
    Abstract: A semiconductor substrate including a single-crystal mono-crystalline film on an insulating film and methods of fabrication are provided. The insulating film has an opening to expose the single-crystal material to a polycrystalline or amorphous semiconductor layer on the insulating film for growing mono-crystals upon application of heat slightly less than the melting point of the semiconductor and applying an energy beam, such as an electron beam or light beam to the semiconductor film. The semiconductor-insulator-semiconductor provides improved substitutes for Silicon On Sapphire formed by the epitaxial method.
    Type: Grant
    Filed: April 16, 1985
    Date of Patent: March 18, 1986
    Assignee: Kabushiki Kaisha Suwa Seikosha
    Inventor: Seiichi Iwamatsu
  • Patent number: 4538291
    Abstract: An X-ray source for producing high intensity X-rays. The X-ray source includes a vessel filled with an inert gas. An energizing mechanism such as a magnetic coil causes the gas to enter a pinch, plasma state which produces high intensity X-rays. The vessel includes a window through which the X-rays are radiated. In a second embodiment, a laser or electron beam bombards a crystal of selected material to produce the X-rays. The material, when gasified, does not interfere with radiation of the X-rays.
    Type: Grant
    Filed: November 2, 1982
    Date of Patent: August 27, 1985
    Assignee: Kabushiki Kaisha Suwa Seikosha
    Inventor: Seiichi Iwamatsu
  • Patent number: 4404236
    Abstract: A process for carrying out chemical vapor deposition under increased pressure is provided. By carrying out chemical vapor deposition under increased pressure, a boundry layer of reduced thickness is formed which permit formation of a chemical vapor reaction film in the minute necking portions on the surface of the substrate formed during formation of the electrical components, such as a transistor or an integrated circuit. The step of chemical vapor deposition under increased pressure may be followed by chemical vapor deposition at normal or reduced pressure for forming a film of uniform thickness across the wafer.
    Type: Grant
    Filed: October 23, 1981
    Date of Patent: September 13, 1983
    Assignee: Kabushiki Kaisha Suwa Seikosha
    Inventors: Shoichi Komatsu, Seiichi Iwamatsu
  • Patent number: 4401738
    Abstract: An X-ray mask including a pattern of X-ray absorbing material on a thin membrane is provided. The mask includes overlapping first and second patterns of X-ray absorbing material. This permits X-ray lithography printing of lines in complex patterns required for large scale integration. The X-ray mask can provide patterns of less than 20 A in thickness by X-ray irradiation.
    Type: Grant
    Filed: November 16, 1981
    Date of Patent: August 30, 1983
    Assignee: Kabushiki Kaisha Suwa Seikosha
    Inventor: Seiichi Iwamatsu
  • Patent number: RE33096
    Abstract: A semiconductor substrate including a single-crystal mono-crystalline film on an insulating film and methods of fabrication are provided. The insulating film has an opening to expose the single-crystal material to a polycrystalline or amorphous semiconductor layer on the insulating film for growing mono-crystals upon application of heat slightly less than the melting point of the semiconductor and applying an energy beam, such as an electron beam or light beam to the semiconductor film. The semiconductor-insulator-semiconductor provides improved substitutes for Silicon On Sapphire formed by the epitaxial method.
    Type: Grant
    Filed: March 17, 1988
    Date of Patent: October 17, 1989
    Assignee: Seiko Epson Corporation
    Inventor: Seiichi Iwamatsu