Patents by Inventor Seiichi Kawano

Seiichi Kawano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080052777
    Abstract: A method for managing shared passwords on a multi-user computer system is disclosed. A set of shared passwords and an administrator internal key are initially generated. After the receipt of an administrator external key, the administrator internal key is encrypted with the administrator external key. For each user level within the computer system, an internal key is generated by hashing the administrator internal key. For each user level within the computer system, each of the shared passwords encrypted with a respective one of the internal keys. The internal keys and the encrypted shared passwords are then stored in a non-volatile storage device.
    Type: Application
    Filed: August 28, 2006
    Publication date: February 28, 2008
    Inventors: Seiichi Kawano, Tadanobu Inoue, David C. Challener, Philip L. Childs, Norman A. Dion
  • Patent number: 7328333
    Abstract: A computer system which includes a CPU for performing various processes by program control and storage elements which store at least one operating system and a BIOS, wherein upon starting a system, the CPU recognizes the system's own hardware configuration, and starts a selected one operating system stored in the storage elements in accordance with the recognized hardware configuration under the control of the BIOS.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: February 5, 2008
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: Seiichi Kawano, Kenneth Blair Ocheltree, Robert Stephen Olyha, Jr.
  • Publication number: 20080022099
    Abstract: Methods and apparatus are provided for securely inputting highly confidential information, exchanging the information via a network, and securely reflecting the information in a computer, without the information being stolen by malicious software. Upon a transfer of encrypted information from a server to a computer, the transferred information is stored in a memory of the computer and the computer is switched to a suspended state and immediately thereafter returns-to the previous state to be shifted to under the control of a BIOS. The information stored in the memory is decrypted and processed there. Processing information generated based on the processed information is then encrypted and it is transferred to the server after the computer is switched to under the control of the operating system.
    Type: Application
    Filed: July 18, 2007
    Publication date: January 24, 2008
    Applicant: Lenovo (Singapore) Pte. Ltd
    Inventors: Seiichi Kawano, Tadanobu Inoue
  • Patent number: 7308587
    Abstract: A computer apparatus provides control for automatically switching the apparatus between various operating modes requiring varying levels of power consumption. An embedded controller determines whether or not the computer apparatus is in motion (vibration, acceleration, rotation, etc.) on the basis of acceleration information obtained through an accelerometer provided in the computer apparatus. If the computer apparatus is in motion, the embedded controller provides control so as to prevent switching between system operating modes in order to protect certain components of the apparatus from damage which might be caused by switching operating modes while in motion.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: December 11, 2007
    Assignee: International Business Machines Corporation
    Inventors: Takashi Inui, Seiichi Kawano, Masahiko Nomura, Shinji Matsushima
  • Patent number: 7254727
    Abstract: An information processor having a normal-operation mode in which coherence control is performed for making data in a cache memory of a processor identical to data in a main memory and a power-saving mode in which the coherence control is suppressed to lower the power consumption from power consumption in the normal-operation mode and entering the normal-operation mode when an input/output device accesses the main memory in the power-saving mode includes an attribute setting module for setting a device area of the main memory, accessed by the input/output device of the information processor to a non-cacheable attribute for exempting said device area from said coherence control even in the normal-operation mode; an operation mode setting module for allowing the input/output device to access the device area while keeping the operation mode of the information processor in the power-saving mode when the input/output device requests access to the device area in the power-saving mode.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: August 7, 2007
    Assignee: Lenovo Singapore Pte Ltd
    Inventors: Noritoshi Yoshiyama, Seiichi Kawano, Hirohide Komiyama, Tetsuji Nakamura
  • Patent number: 7225346
    Abstract: There is provided an information processor including a central processing unit that includes an instruction execution module and has a normal mode for operating the instruction execution module and an execution halt mode for halting the instruction execution module.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: May 29, 2007
    Assignee: Lenovo Singapore Pte. Ltd
    Inventors: Seiichi Kawano, Shinji Matsushima
  • Patent number: 7225352
    Abstract: An information processor includes a power-saver which switches a display memory to a power-saving state that causes image data to be lost and restores the display memory from the power-saving state. A storage area stores a predetermined activation condition and an activation routine mechanism activates a predetermined routine when the activation condition is satisfied. A routine termination mechanism ends the routine and an image data re-creation mechanism executes re-creation of the image data on the display memory when the routine is terminated. Provided are: an activation condition rewriting mechanism which rewrites the activation condition stored in the storage area so that the routine is activated when the display memory is switched to or restored from the power-saving state; and an activation condition restoration mechanism which restores the rewritten activation condition to the original condition after the routine is activated.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: May 29, 2007
    Assignee: Lenovo (Singapore) Pte. Ltd
    Inventors: Seiichi Kawano, Toyoaki Inada, Norihito Ishida, Yasumasa Takeda
  • Patent number: 7203804
    Abstract: A process, apparatus, and system are disclosed that allow information to be passed between software modules in different partitions in an environment for a predetermined operating system (OS) and an area hidden from the operating system (OS) in a storage device, such as hard disk drive (HDD). The computer system may include a hard disk drive (HDD) that meets a protected area run time interface extension services (PARTIES) specification and that has an access environment for an operating system (OS) and a PARTIES partition. The PARTIES partition is an area hidden from the operating system (OS). The computers system also includes a CMOS/NVRAM that provides a work area for communication between a user mode module, operating in the access environment for the operating system (OS) in a user data management application, and a management mode module, operating in an environment corresponding to the hidden area.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: April 10, 2007
    Assignee: International Business Machines Corporation
    Inventors: Seiichi Kawano, Ken Sasaki, Mikio Hagiwara, Kishiko Itoh
  • Patent number: 7181634
    Abstract: An information processor having a plurality of operating modes differing in power consumption and capable of changing the operating mode according to the amount of processing has periodic switching detection means of performing detection as to whether the information processor is periodically switching from a low-power-consumption operating mode in which the power consumption is lower to a high-power-consumption operating mode in which the power consumption is higher in the plurality of operating modes, and operating mode changing means of changing the operating modes between which the information processor switches to a combination of the operating modes such that the difference between the power consumptions is reduced relative to that at the time of switching between the low-power-consumption operating mode and the high-power-consumption operating mode if the switching cycle detected by the periodic switching detection means is shorter than a set cycle determined in advance.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: February 20, 2007
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: Takayuki Katoh, Seiichi Kawano, Kenji Oka, Noritishi Yoshiyama
  • Patent number: 7167992
    Abstract: An information processor having a plurality of operating modes differing in power consumption and capable of changing the operating mode according to the amount of processing has periodic switching detection means of performing detection as to whether the information processor is periodically switching from a low-power-consumption operating mode in which the power consumption is lower to a high-power-consumption operating mode in which the power consumption is higher in the plurality of operating modes, and operating mode changing means of changing the operating modes between which the information processor switches to a combination of the operating modes such that the difference between the power consumptions is reduced relative to that at the time of switching between the low-power-consumption operating mode and the high-power-consumption operating mode if the switching cycle detected by the periodic switching detection means is shorter than a set cycle determined in advance.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: January 23, 2007
    Assignee: Lenovo Singapore Pte, Ltd.
    Inventors: Takayuki Katoh, Seiichi Kawano, Kenji Oka, Noritishi Yoshiyama
  • Publication number: 20070016786
    Abstract: A method for updating an ISO file, e.g., to add a digital signature to the ISO file, includes adding a supplemental file composed of, e.g., all zeroes to the ISO file before recording, and then recording the ISO file with supplemental file to an optical disk using ISO format. A digital signature is computed after recording. The zeroes in the supplemental file are replaced by the values of the digital signature and the file is re-saved. Also, an ISO file that might have a common part and several unique parts, e.g., for respective languages, is deconstructed such that only a single copy of the common part is recorded to disk, avoiding multiple recordations of the same data.
    Type: Application
    Filed: July 13, 2005
    Publication date: January 18, 2007
    Inventors: Rod Waltermann, Mark Davis, Seiichi Kawano
  • Patent number: 7119797
    Abstract: Units are provided for determining whether or not a coordinate input is continued as being substantially the same coordinate and a predetermined time period has lapsed after an initial input of an arbitrary coordinate by a coordinate input unit. A first processing unit performs a first processing in accordance with the coordinate when the determination is not met, and a second processing unit performs a second processing different from the first processing when the determination is met.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: October 10, 2006
    Assignee: Lenovo Pte. Ltd.
    Inventors: Seiichi Kawano, Masayoshi Nakano, Yuhko Ohmori
  • Publication number: 20060190745
    Abstract: Power usage of computing device components is controlled in a holistic manner. The projected total power consumption for the computing device to satisfy a power consumption policy for the device is determined. Power usage of each component of the computing device is controlled in a holistic manner—i.e., balancing the power usage of the component against the power usage of other components—so that the total power usage of the computing device falls within the projected total power consumption needed to satisfy the power consumption policy. How the user is currently utilizing the computing device may be periodically detected, based at least on a power consumption distribution of the components of the computing device. A current usage model is determined based on how the user is currently utilizing the computing device. The power usage of each component of the computing device is controlled based on the current usage model.
    Type: Application
    Filed: February 18, 2005
    Publication date: August 24, 2006
    Inventors: Shinji Matsushima, Yasumichi Tsukamoto, Mitsuhiro Yamazaki, Seiichi Kawano
  • Patent number: 7081886
    Abstract: A touch panel that improves operability for users is provided. The touch panel monitors and calibrates operation positions made by a user on a display screen is provided, including a mark display part that displays marks indicating operation target positions on the display screen such that the densities of the marks in the main scanning line direction or sub-scanning line direction are different in response to positions of the directions; an operation position reader part that reads operation positions on the touch panel by the user; a relative position acquisition part that obtains relative positions of the operation positions from the mark made by the user relative to a display position of the mark; and a calibration part that calibrates the position of a new operation by the user different from an operation applied to the mark based on the relative positions.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: July 25, 2006
    Assignee: Lenovo (Singapore) PTE Ltd.
    Inventors: Masayoshi Nakano, Seiichi Kawano
  • Publication number: 20060136708
    Abstract: A method for is disclosed. A boot block that contains a first public key is activated and a system Basic Input/Output System (BIOS) that contains a second public key and a first digital signature is verified, the verifying being performed by confirming that the first and second public keys match. In response to a determination that the first and second public keys match, the BIOS is activated and a system image is loaded to a real device. The system image is verified by confirming that the first digital signature that is stored in the system BIOS matches a second digital signature that is stored in a mass storage device. In response to the first and second digital signatures matching, a virtual mass storage device is created. Control of the virtual mass storage device is transferred to a boot strap code in an operating system image and the operating system image is booted from the virtual mass storage device.
    Type: Application
    Filed: December 19, 2005
    Publication date: June 22, 2006
    Inventors: Hassan Hajji, Seiichi Kawano, Masana Murase, Susumu Shimotono
  • Publication number: 20060095902
    Abstract: Devices, compilers and methods to reduce energy consumption associated with execution of a program by adjusting a computational capability of a CPU with higher accuracy than before. A device sets an appropriate computational capability to the CPU. It includes: changing a computational capability of the CPU every time each of a plurality of program areas included in the execution program is executed while the execution program is being executed, and measuring execution time each of the program areas; deciding an optimal computational capability required to execute the program area using the CPU, based on the execution time for each of the computational capabilities measured for the respective program areas; and performing setting of the optimal computational capability for executing the program area, which is to be used when executing the program area again in the course of executing the execution program, for each of the program areas.
    Type: Application
    Filed: October 20, 2005
    Publication date: May 4, 2006
    Applicant: International Business Machines Corporation
    Inventors: Takuya Nakaike, Hideaki Komatsu, Seiichi Kawano
  • Publication number: 20060075476
    Abstract: An information processing apparatus includes a storage device having an access-restricted area accessible if the password is properly authenticated and an access-unrestricted area accessible regardless of whether or not the password is authenticated. The information processing apparatus allows a password to be registered in a registration server beforehand, prompts a user to enter the password when accessing the access-restricted area and, if the password is not entered, reads from the access-unrestricted area a password retrieval program for retrieving the password from the registration server, activates and executes the password retrieval program to retrieve the password from the registration server, and causes the storage device to authenticate the retrieved password to place the access-restricted area in an accessible state.
    Type: Application
    Filed: August 26, 2005
    Publication date: April 6, 2006
    Inventors: Hassan Hajji, Seiichi Kawano, Masana Murase, Susumu Shimetono
  • Patent number: 6992660
    Abstract: An apparatus, program product and method of detecting, within a predetermined time period after an input of a first coordinate, an input of a second coordinate being apart a predetermined distance or more from a first coordinate, or detecting, within a predetermined time period after an input of the first coordinate, an input of the second coordinate being apart a predetermined distance or more from the first coordinate and the following input of a third coordinate near the first coordinate, whereby a first processing in accordance with the first coordinate or a second processing in accordance with the first coordinate is performed depending on the detected result.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: January 31, 2006
    Assignee: Lenovo (Singapore) Pte Ltd
    Inventors: Seiichi Kawano, Masayoshi Nakano, Yuhko Ohmori
  • Publication number: 20050138449
    Abstract: An information processor having a plurality of operating modes differing in power consumption and capable of changing the operating mode according to the amount of processing has periodic switching detection means of performing detection as to whether the information processor is periodically switching from a low-power-consumption operating mode in which the power consumption is lower to a high-power-consumption operating mode in which the power consumption is higher in the plurality of operating modes, and operating mode changing means of changing the operating modes between which the information processor switches to a combination of the operating modes such that the difference between the power consumptions is reduced relative to that at the time of switching between the low-power-consumption operating mode and the high-power-consumption operating mode if the switching cycle detected by the periodic switching detection means is shorter than a set cycle determined in advance.
    Type: Application
    Filed: December 18, 2003
    Publication date: June 23, 2005
    Applicant: International Business Machines Corporation
    Inventors: Takayuki Katoh, Seiichi Kawano, Kenji Oka, Noritoshi Yoshiyama
  • Publication number: 20050060591
    Abstract: An information processor having a normal-operation mode in which coherence control is performed for making data in a cache memory of a processor identical to data in a main memory and a power-saving mode in which the coherence control is suppressed to lower the power consumption from power consumption in the normal-operation mode and entering the normal-operation mode when an input/output device accesses the main memory in the power-saving mode includes an attribute setting module for setting a device area of the main memory, accessed by the input/output device of the information processor to a non-cacheable attribute for exempting said device area from said coherence control even in the normal-operation mode; an operation mode setting module for allowing the input/output device to access the device area while keeping the operation mode of the information processor in the power-saving mode when the input/output device requests access to the device area in the power-saving mode.
    Type: Application
    Filed: December 8, 2003
    Publication date: March 17, 2005
    Applicant: International Business Machines Corporation
    Inventors: Noritoshi Yoshiyama, Seiichi Kawano, Hirohide Komiyama, Tetsuji Nakamura