Patents by Inventor Seiichiro Kihara

Seiichiro Kihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220334169
    Abstract: In this testing device, a space in which a transistor 117 is disposed and a space in which a driving circuit for testing is disposed are separated by a partition wall 214. The driving circuit has a plurality of switch circuit boards 201, and a conductive plate 204 for connection is attached to the switch circuit board 201. A fork plug 205e is connected to a collector c terminal of the transistor 117 to be tested, and a fork plug 205c is connected to an emitter e terminal. The insertion of the fork plug 205 into an opening 216 provided in the partition wall 214 allows the connection of the fork plug 205 and the conductive plate 204. By changing the position of the opening 216 for inserting the fork plug 205, the connection to the driving circuit can be changed in accordance with an item to be tested.
    Type: Application
    Filed: May 25, 2020
    Publication date: October 20, 2022
    Applicant: Qualtec Co., Ltd.
    Inventors: Shigeo Sakata, Takahiro Kajinishi, Seiichiro Kihara, Hiroshi Takahara
  • Patent number: 10707204
    Abstract: A composite semiconductor device with improved response performance and reliability is provided while an increase in wiring area being suppressed. Fingers 1 are arranged in a plurality of rows and a plurality of columns. A signal inputted via a gate terminal (3) is supplied from intermediate regions in a row-wise direction of gate wires (18) connected to gate electrodes (G) of the same row or two adjacent rows of fingers 1 of the fingers 1 and formed along the rows.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 7, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Seiichiro Kihara
  • Patent number: 10651143
    Abstract: Provided is an electrode like a protruding electrode that is self-standing on a substrate. A conductive paste (202) contains a conductive powder, an alcoholic liquid component, and no adhesives. The conductive powder contains conductive particles having a thickness of 0.05 ?m or more and 0.1 ?m or less and a representative length of 5 ?m or more and 10 ?m or less, the representative length being a maximum diameter in a plane perpendicular to the direction of the thickness. The weight percentage of the alcoholic liquid component relative to the conductive paste is 8% or more and 20% or less.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: May 12, 2020
    Assignees: SHARP KABUSHIKI KAISHA, OSAKA UNIVERSITY
    Inventors: Tomotoshi Satoh, Hiroya Sato, Katsuaki Suganuma, Aiji Suetake, Shijo Nagao, Jinting Jiu, Seiichiro Kihara
  • Publication number: 20190157229
    Abstract: Provided is an electrode like a protruding electrode that is self-standing on a substrate. A conductive paste (202) contains a conductive powder, an alcoholic liquid component, and no adhesives. The conductive powder contains conductive particles having a thickness of 0.05 ?m or more and 0.1 ?m or less and a representative length of 5 ?m or more and 10 ?m or less, the representative length being a maximum diameter in a plane perpendicular to the direction of the thickness. The weight percentage of the alcoholic liquid component relative to the conductive paste is 8% or more and 20% or less.
    Type: Application
    Filed: April 28, 2017
    Publication date: May 23, 2019
    Applicants: Sharp Kabushiki Kaisha, Osaka University
    Inventors: Tomotoshi SATOH, Hiroya SATO, Katsuaki SUGANUMA, Aiji SUETAKE, Shijo NAGAO, Jinting JIU, Seiichiro KIHARA
  • Publication number: 20180197855
    Abstract: A composite semiconductor device with improved response performance and reliability is provided while an increase in wiring area being suppressed. Fingers 1 are arranged in a plurality of rows and a plurality of columns. A signal inputted via a gate terminal (3) is supplied from intermediate regions in a row-wise direction of gate wires (18) connected to gate electrodes (G) of the same row or two adjacent rows of fingers 1 of the fingers 1 and formed along the rows.
    Type: Application
    Filed: March 31, 2016
    Publication date: July 12, 2018
    Inventor: SEIICHIRO KIHARA
  • Publication number: 20180040601
    Abstract: Provided is a lateral field effect transistor in which response performance is improved. In a lateral field effect transistor, a block is arranged closer to a gate terminal than a Zener diode.
    Type: Application
    Filed: February 16, 2016
    Publication date: February 8, 2018
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Seiichiro KIHARA
  • Patent number: 9742388
    Abstract: A driver circuit includes normally-on transistors (Q1, Q2), control circuits (1, 2) that control the transistors (Q1, Q2), a capacitor (4) connected between power source nodes (1c, 1d) of the control circuit (1), a power source (7) connected between power source nodes (2c, 2d) of the control circuit (2), a MOSFET (16) connected between the power source nodes (1d, 2d), a control circuit (3) that turns on the MOSFET (16) when an output voltage VO reaches approximately 0 V, and a startup circuit that includes a Zener diode (20) connected in parallel to the capacitor (4) and that can charge the capacitor (4) with a Zener voltage even when the MOSFET (16) is off.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: August 22, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Seiichiro Kihara
  • Publication number: 20170093389
    Abstract: A driver circuit includes normally-on transistors (Q1, Q2), control circuits (1, 2) that control the transistors (Q1, Q2), a capacitor (4) connected between power source nodes (1c, 1d) of the control circuit (1), a power source (7) connected between power source nodes (2c, 2d) of the control circuit (2), a MOSFET (16) connected between the power source nodes (1d, 2d), a control circuit (3) that turns on the MOSFET (16) when an output voltage VO reaches approximately 0 V, and a startup circuit that includes a Zener diode (20) connected in parallel to the capacitor (4) and that can charge the capacitor (4) with a Zener voltage even when the MOSFET (16) is off.
    Type: Application
    Filed: February 17, 2015
    Publication date: March 30, 2017
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Seiichiro KIHARA
  • Patent number: 9397563
    Abstract: A driver circuit includes normally-on first and second transistors, a first control circuit for controlling the first transistor in response to a first control signal, a second control circuit for controlling the second transistor in response to a second control signal, a capacitor connected between first and second power supply nodes of the first control circuit, a power supply connected between third and fourth power supply nodes of the second control circuit, a switch element connected between first and fourth power supply nodes, and a third control circuit for turning the switch element on when an output voltage becomes about 0V.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: July 19, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Seiichiro Kihara, Akio Nakajima
  • Patent number: 9264022
    Abstract: Provided is a high-reliability level shift circuit not prone to faulty operation due to noise.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: February 16, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Seiichiro Kihara
  • Publication number: 20150358003
    Abstract: Provided is a high-reliability level shift circuit not prone to faulty operation due to noise.
    Type: Application
    Filed: February 27, 2014
    Publication date: December 10, 2015
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Seiichiro KIHARA
  • Publication number: 20150207428
    Abstract: An inverter drive circuit is equipped with a switching element for each of the upper and lower arms connected in series between the positive electrode and the negative electrode of a DC power source, and a driver circuit for controlling the switching on and off of the switching elements, according to a control signal imparted to each of the switching elements, has a load connected to the connection point between the switching elements of the upper and lower arms, converts the DC-power-source power into AC through the switching on and off, and supplies said power to the load. Therein, the driver circuit compares the voltage of each terminal at both ends of the switching elements, and controls on the basis of the comparison result and the control signal.
    Type: Application
    Filed: June 27, 2013
    Publication date: July 23, 2015
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Seiichiro Kihara
  • Patent number: 8971071
    Abstract: The present invention provides a safe circuit that can prevent an arm short, when a half-bridge circuit is configured by using a normally-on switching element, and the half-bridge circuit is used as a driver circuit or an inverter circuit. In a driver circuit configured by a half-bridge circuit in which one of input and output terminals of a first switching element 14 is connected to a first power-supply voltage V1 on a high-voltage side, and the first switching element 14 and a second switching element 15 are connected in series, a normally-off third switching element 16 is inserted between the second switching element 15 and a second power-supply voltage V2 on a low voltage side. The third switching element 16 is turned off, when an operating voltage VH or VL supplied from control-circuit power supplies 13a and 13b is insufficient for the operation of a control circuit 11.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: March 3, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Seiichiro Kihara
  • Patent number: 8957721
    Abstract: The present invention provides a level shift circuit having low possibility of malfunction by noise, and can operate with low power.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: February 17, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Seiichiro Kihara, Shunichi Utsumi
  • Patent number: 8952730
    Abstract: A gate driver circuit that can supply a negative gate voltage to a high-side circuit without being additionally provided with an insulated power supply is realized. A driver circuit is configured such that a half-bridge circuit in which a first transistor and a second transistor are connected in series includes a capacitor that supplies a negative gate voltage to a high-side first transistor via a first control circuit, and a control circuit power supply that supplies a negative gate voltage to a low-side second transistor via a second control circuit, one end of the capacitor being connected to a negative voltage VEE on a negative terminal side of the control circuit power supply via a switching element, and the other end being connected to a voltage on an output terminal, wherein the switching element is controlled to be on upon a timing when the second transistor is turned on.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: February 10, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Seiichiro Kihara, Akio Nakajima
  • Publication number: 20140375292
    Abstract: A driver circuit includes normally-on first and second transistors, a first control circuit for controlling the first transistor in response to a first control signal, a second control circuit for controlling the second transistor in response to a second control signal, a capacitor connected between first and second power supply nodes of the first control circuit, a power supply connected between third and fourth power supply nodes of the second control circuit, a switch element connected between first and fourth power supply nodes, and a third control circuit for turning the switch element on when an output voltage becomes about 0V.
    Type: Application
    Filed: December 17, 2012
    Publication date: December 25, 2014
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Seiichiro Kihara, Akio Nakajima
  • Publication number: 20140347116
    Abstract: A level shift circuit of an embodiment includes first and second MOSFETs using signals with phases same as and opposite to the phase of an input signal as gate inputs; first and second resistance elements, each having one end connected to a shift level power terminal that supplies high-level output voltage of a level-shifted output signal, and each having the other end connected to a corresponding drain of the first and second MOSFETs; a comparator having a pair of differential input terminals, individually connected to respective drains of the first and second MOSFETs; and a current control circuit that controls an amount of first current flowing through the first MOSFET via the first resistance element and an amount of second current flowing through the second MOSFET via the second resistance element in synchronization with a rising and a falling of a signal level of the input signal.
    Type: Application
    Filed: July 27, 2012
    Publication date: November 27, 2014
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Seiichiro Kihara, Shunichi Utsumi
  • Publication number: 20130215653
    Abstract: The present invention provides a safe circuit that can prevent an arm short, when a half-bridge circuit is configured by using a normally-on switching element, and the half-bridge circuit is used as a driver circuit or an inverter circuit. In a driver circuit configured by a half-bridge circuit in which one of input and output terminals of a first switching element 14 is connected to a first power-supply voltage V1 on a high-voltage side, and the first switching element 14 and a second switching element 15 are connected in series, a normally-off third switching element 16 is inserted between the second switching element 15 and a second power-supply voltage V2 on a low voltage side. The third switching element 16 is turned off, when an operating voltage VH or VL supplied from control-circuit power supplies 13a and 13b is insufficient for the operation of a control circuit 11.
    Type: Application
    Filed: September 26, 2011
    Publication date: August 22, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Seiichiro Kihara
  • Publication number: 20130200926
    Abstract: A gate driver circuit that can supply a negative gate voltage to a high-side circuit without being additionally provided with an insulated power supply is realized. A driver circuit is configured such that a half-bridge circuit in which a first transistor and a second transistor are connected in series includes a capacitor that supplies a negative gate voltage to a high-side first transistor via a first control circuit, and a control circuit power supply that supplies a negative gate voltage to a low-side second transistor via a second control circuit, one end of the capacitor being connected to a negative voltage VEE on a negative terminal side of the control circuit power supply via a switching element, and the other end being connected to a voltage on an output terminal, wherein the switching element is controlled to be on upon a timing when the second transistor is turned on.
    Type: Application
    Filed: July 25, 2011
    Publication date: August 8, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Seiichiro Kihara, Akio Nakajima
  • Publication number: 20070083731
    Abstract: An ID determining portion determines a self processor ID according to an input port name receiving a control instruction and a sender processor ID stored in the received control instruction. The control instruction storing the self processor ID is output from each output port via a diverging portion. Therefore, the processor ID of each processor can be automatically determined during initializing processing.
    Type: Application
    Filed: September 19, 2006
    Publication date: April 12, 2007
    Inventor: Seiichiro Kihara