Patents by Inventor Seiji Mochizuki

Seiji Mochizuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9906805
    Abstract: In an image processing device, a motion image decoding processing unit extracts a feature amount of a target image to be decoded from an input stream, and changes a read size of a cache fill from an external memory to a cache memory, based on the feature amount. The feature amount represents an intra macro block ratio in, for example, one picture (frames or fields), or a motion vector variation. When the intra macro block ratio is high, the read size of the cache fill is decreased.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: February 27, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Keisuke Matsumoto, Katsushige Matsubara, Seiji Mochizuki, Toshiyuki Kaya, Hiroshi Ueda
  • Patent number: 9877044
    Abstract: To reduce noise or the like generated at a boundary of tiles introduced in a video coding method. In a motion vector detection unit, a first tile video signal and a second tile video signal included in one picture are supplied to a first detection unit and a second detection unit, and a reference image is supplied from a frame memory to the first detection unit and the second detection unit. The first detection unit performs processing, by inter prediction, on the video signal positioned on or in the vicinity of a tile boundary between a first tile and another tile among many video signals included in the first tile. In this processing, the first detection unit generates a motion vector so as to preferentially refer to the reference image included in another tile different from the first tile among the reference images read out from the frame memory.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: January 23, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Iwata, Seiji Mochizuki, Toshiyuki Kaya, Ryoji Hashimoto
  • Publication number: 20170366817
    Abstract: In terms of the transmission of the coding method, it is ensured to decode information coded according to the intra-frame prediction coding with vector information. An error of a piece of divisional image information targeted for image prediction coding and a piece of predicted information is determined to perform prediction coding. A data stream in which a piece of information for identifying a prediction method and a piece of information subjected to prediction coding according to the method are arranged is produced according to the process sequence of the prediction coding for each process on the divisional image information. At this time, the data stream has a pair of vector information and the error information as information subjected to prediction coding for each process on the divisional image information on condition that the prediction method is intra-frame prediction coding with vectors.
    Type: Application
    Filed: September 6, 2017
    Publication date: December 21, 2017
    Inventors: Ryoji HASHIMOTO, Seiji MOCHIZUKI, Kenichi IWATA
  • Patent number: 9832483
    Abstract: To reduce noise or the like generated at a boundary of tiles introduced in a video coding method. In a motion vector detection unit, a first tile video signal and a second tile video signal included in one picture are supplied to a first detection unit and a second detection unit, and a reference image is supplied from a frame memory to the first detection unit and the second detection unit. The first detection unit performs processing, by inter prediction, on the video signal positioned on or in the vicinity of a tile boundary between a first tile and another tile among many video signals included in the first tile. In this processing, the first detection unit generates a motion vector so as to preferentially refer to the reference image included in another tile different from the first tile among the reference images read out from the frame memory.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: November 28, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Iwata, Seiji Mochizuki, Toshiyuki Kaya, Ryoji Hashimoto
  • Publication number: 20170337008
    Abstract: There is a problem that memory protection against access to a shared memory by a sub-arithmetic unit used by a program executed in a main-arithmetic unit cannot be performed in a related-art semiconductor device. According to one embodiment, a semiconductor device includes a sub-arithmetic unit configured to execute a process of a part of a program executed by a main-arithmetic unit, and a shared memory shared by the main-arithmetic unit and the sub-arithmetic unit, in which the sub-arithmetic unit includes a memory protection unit configured to permit or prohibit access to the shared memory based on an access permission range address value provided from the main-arithmetic unit, the access to the shared memory being access that arises from a process executed by the sub-arithmetic unit.
    Type: Application
    Filed: April 28, 2017
    Publication date: November 23, 2017
    Inventors: Seiji MOCHIZUKI, Katsushige Matsubara, Ren Imaoka, Hiroshi Ueda, Ryoji Hashimoto, Toshiyuki Kaya
  • Patent number: 9813703
    Abstract: A compressed dynamic image encoding device is provided, in which a motion vector is generated by searching a reference image for an image area most similar to an image area of a video input signal; a motion-compensated reference image is generated from the motion vector and the reference image; a prediction residual is generated, by subtracting the motion-compensated reference image from the video input signal; the reference image is generated, by adding the motion-compensated reference image and the result of processing performed to the prediction residual; and an encoded video output signal is generated by the processing performed to the prediction residual. The reference image comprises on-screen reference images, located inside a video display screen, and an off-screen reference image located outside the video display screen, and the off-screen reference image is generated based on the positional relationship of plural similar reference images of the on-screen reference images.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: November 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Seiji Mochizuki, Junichi Kimura, Masakazu Ehama
  • Publication number: 20170311001
    Abstract: An image encoding device includes an encoding circuit configured to encode an image, the image being constituted of a plurality of columns and a plurality of rows of which width are longer than the columns, generate a reference image and stores the reference image into a memory, and output a bit stream including the encoded image. The image encoding device also includes an image rotation circuit configured to rotate the image read from the memory by 90° and output the rotated image to a encoding processing circuit, and a read address generating circuit configured to read the column of the image from the memory, and provide the column with the image rotation circuit.
    Type: Application
    Filed: July 12, 2017
    Publication date: October 26, 2017
    Inventors: Seiji Mochizuki, Kazushi Akie, Tetsuya Shibayama, Kenichi Iwata
  • Patent number: 9787981
    Abstract: In terms of the transmission of the coding method, it is ensured to decode information coded according to the intra-frame prediction coding with vector information. An error of a piece of divisional image information targeted for image prediction coding and a piece of predicted information is determined to perform prediction coding. A data stream in which a piece of information for identifying a prediction method and a piece of information subjected to prediction coding according to the method are arranged is produced according to the process sequence of the prediction coding for each process on the divisional image information. At this time, the data stream has a pair of vector information and the error information as information subjected to prediction coding for each process on the divisional image information on condition that the prediction method is intra-frame prediction coding with vectors.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: October 10, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Ryoji Hashimoto, Seiji Mochizuki, Kenichi Iwata
  • Publication number: 20170280155
    Abstract: To reduce noise or the like generated at a boundary of tiles introduced in a video coding method. In a motion vector detection unit, a first tile video signal and a second tile video signal included in one picture are supplied to a first detection unit and a second detection unit, and a reference image is supplied from a frame memory to the first detection unit and the second detection unit. The first detection unit performs processing, by inter prediction, on the video signal positioned on or in the vicinity of a tile boundary between a first tile and another tile among many video signals included in the first tile. In this processing, the first detection unit generates a motion vector so as to preferentially refer to the reference image included in another tile different from the first tile among the reference images read out from the frame memory.
    Type: Application
    Filed: June 9, 2017
    Publication date: September 28, 2017
    Inventors: Kenichi IWATA, Seiji MOCHIZUKI, Toshiyuki KAYA, Ryoji HASHIMOTO
  • Publication number: 20170264820
    Abstract: A semiconductor device includes: an encoding processing unit that stores an encoded stream of an input data that is encoded based on the specified encoding control information; a buffer management unit that calculates the transmission buffer occupancy indicating the amount of data stored in a transmission buffer according to the generated data amount, and the reception buffer occupancy indicating the amount of data stored in a reception buffer, which is the destination of the encoded stream; and a control information specifying unit that, when the transmission buffer occupancy is equal to or less than a first threshold, specifies the encoding control information based on the reception buffer occupancy, and when the transmission buffer occupancy is greater than the first threshold, specifies the encoding control information to further reduce the generated data amount than in the case of equal to or less than the first threshold, to the encoding processing unit.
    Type: Application
    Filed: February 1, 2017
    Publication date: September 14, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Tetsuya SHIBAYAMA, Toshiyuki KAYA, Seiji MOCHIZUKI, Ryoji HASHIMOTO
  • Publication number: 20170257637
    Abstract: An in-vehicle system includes a camera having an encoder encoding video obtained by the camera, an image processing apparatus which receives the encoded video from the camera, and an image recognition processing circuit performing image recognition on decoded video data from the image processing apparatus. The image processing apparatus includes a codec processing circuit which decodes the encoded video, a plurality of image processing circuits which execute tasks in parallel, an estimating circuit which estimates estimation time in which a process of the task is completed in each of the image processing circuit on the basis of the number of access times to a bus which is obtained on the basis of a parameter of decoding used in the codec processing circuit, and a scheduling circuit which schedules tasks to be executed by the plurality of image processing circuit on the basis of the estimation time.
    Type: Application
    Filed: May 24, 2017
    Publication date: September 7, 2017
    Inventors: Katsushige MATSUBARA, Takayuki MATSUMI, Seiji MOCHIZUKI, Kenichi IWATA, Toshiyuki KAYA
  • Patent number: 9712842
    Abstract: To reduce noise or the like generated at a boundary of tiles introduced in a video coding method. In a motion vector detection unit, a first tile video signal and a second tile video signal included in one picture are supplied to a first detection unit and a second detection unit, and a reference image is supplied from a frame memory to the first detection unit and the second detection unit. The first detection unit performs processing, by inter prediction, on the video signal positioned on or in the vicinity of a tile boundary between a first tile and another tile among many video signals included in the first tile. In this processing, the first detection unit generates a motion vector so as to preferentially refer to the reference image included in another tile different from the first tile among the reference images read out from the frame memory.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: July 18, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Iwata, Seiji Mochizuki, Toshiyuki Kaya, Ryoji Hashimoto
  • Publication number: 20170185521
    Abstract: Bus/memory bandwidth consumption caused by reading of auxiliary information not included in compressed data is reduced. A memory stores compressed data and auxiliary information used to read the compressed data. A semiconductor device includes a cache in which auxiliary information stored in the memory is stored, a control unit which, when a read request for reading compressed data stored in the memory is received, reads from the cache auxiliary information about the compressed data, if stored in the cache, or reads the auxiliary information about the compressed data, if not stored in the cache, from the memory and stores the auxiliary information about the compressed data in the cache, and which reads the compressed data from the memory using the auxiliary information about the compressed data, and an expansion unit to expand the compressed data read from the memory.
    Type: Application
    Filed: November 22, 2016
    Publication date: June 29, 2017
    Inventors: Katsushige MATSUBARA, Keisuke MATSUMOTO, Seiji MOCHIZUKI
  • Publication number: 20170161219
    Abstract: In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced. The semiconductor device includes a CPU section. and a. hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.
    Type: Application
    Filed: November 21, 2016
    Publication date: June 8, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Masaru HASE, Tetsuji TSUDA, Naohiro NISHIKAWA, Yuki INOUE, Seiji MOCHIZUKI, Katsushige MATSUBARA, Ren IMAOKA
  • Publication number: 20170153838
    Abstract: Disclosed is a semiconductor device capable of performing compression and decompression with increased appropriateness. The semiconductor device includes a computing module and a memory control module. The computing module includes a computing unit and a compression circuit. The computing unit performs arithmetic processing. The compression circuit compresses data indicative of the result of arithmetic processing. The memory control module includes an access circuit and a decompression circuit. The access circuit writes compressed data into a memory and reads written data from the memory. The decompression circuit decompresses data read from the memory and outputs the decompressed data to the computing module.
    Type: Application
    Filed: November 18, 2016
    Publication date: June 1, 2017
    Inventors: Katsushige MATSUBARA, Seiji MOCHIZUKI, Ryoji HASHIMOTO, Toshiyuki KAYA, Kimihiko NAKAZAWA, Takahiro IRITA, Tetsuji TSUDA
  • Patent number: 9667983
    Abstract: An image processing apparatus includes a request receiving unit that receives requests from a plurality of pieces of content, a variable-length code processing unit which decodes or encodes the content, a plurality of image signal processing units executing tasks according to the requests in parallel, an estimating unit that estimates estimate time by which a process of the task is completed in each of the image signal processing units on the basis of a parameter of decoding or encoding used in the variable-length code processing unit, and a scheduling unit that schedules tasks executed by the plurality of image signal processing units on the basis of estimation time estimated by the estimating unit.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: May 30, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsushige Matsubara, Takayuki Matsumi, Seiji Mochizuki, Kenichi Iwata, Toshiyuki Kaya
  • Publication number: 20170118468
    Abstract: An image receiving method for a decoder, includes receiving an encoding stream multiplexed into three levels of sequence, picture, and slice, receiving an environmental information of an image receiving device and determining a parameter to be changed in the image encoding stream based on the environmental information of the image receiving device, changing a parameter at the sequence level, changing a parameter at the picture level and at the sequence level for each picture based on information indicating accuracy of image recognition, and statistical information obtained by decoding, and changing a parameter in the slice header based on the information indicating accuracy of image recognition, and the statistical information obtained by decoding.
    Type: Application
    Filed: January 9, 2017
    Publication date: April 27, 2017
    Inventors: Kenichi Iwata, Tetsuya Shibayama, Katsushige Matsubara, Ren Imaoka, Seiji Mochizuki
  • Publication number: 20170094280
    Abstract: A semiconductor device includes a hash generator, a reference hash list, a frame mode determination unit, and an intra prediction unit. The hash generator generates a hash value of a target frame to be encoded. The reference hash list is to record the hash value generated by the hash generator. The frame mode determination unit compares the hash value generated by the hash generator and the hash value in the reference hash list. The intra prediction unit performs intra prediction for the target frame to be encoded. When the hash value of the target frame to be encoded coincides with any of the hash values in the reference hash list, the intra prediction unit skips an encoding process, and outputs encoded information corresponding to any of the hash values in the reference hash list.
    Type: Application
    Filed: September 15, 2016
    Publication date: March 30, 2017
    Inventors: Ren IMAOKA, Seiji MOCHIZUKI, Toshiyuki KAYA, Kazushi AKIE, Ryoji HASHIMOTO
  • Publication number: 20170064312
    Abstract: Making effective use of an image encoder and an image decoder for processing a color image of a general-purpose standard bit depth, an image transmission device capable of transmitting/receiving a monochrome image of a higher bit depth is configured. An image transmission device includes an image encoder to encode a high bit-depth monochrome image and output encoded data and an image decoder to generate, by decoding the encoded data received via a transmission path, a high bit-depth monochrome image. The image encoder decomposes the input high bit-depth image data into plural bit planes corresponding to color image data of a standard bit depth and encodes the standard bit-depth color image data. The image decoder decodes the color image data of the standard bit depth and synthesizes, from the decoded standard bit-depth color image data, a high bit-depth monochrome image.
    Type: Application
    Filed: July 9, 2016
    Publication date: March 2, 2017
    Inventors: Tomohiro UNE, Takahiko SUGIMOTO, Kwangsoo PARK, Toshiyuki KAYA, Tetsuya SHIBAYAMA, Seiji MOCHIZUKI
  • Patent number: 9554137
    Abstract: To improve an image recognition rate by quickly changing a parameter in a proper manner without being affected by a transmission delay of an image encoding stream in an image receiving device that recognizes a decoded image obtained by decoding the received image encoding stream. The image receiving device includes a data receiving unit, a parameter changing unit, a decoding unit, and an image recognition unit. The data receiving unit receives an image encoding stream including image encoding data and the parameter. The parameter changing unit changes the parameter received by the data receiving unit, that is, the parameter specified for encoding performed by a sender, to a value suitable for image recognition performed in the subsequent stage. The decoding unit generates the image decoding data by decoding the received image encoding data according to the changed parameter. The image recognition unit performs image recognition on the image decoding data.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: January 24, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kenichi Iwata, Tetsuya Shibayama, Katsushige Matsubara, Ren Imaoka, Seiji Mochizuki