Patents by Inventor Seiji Munetoh

Seiji Munetoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10313122
    Abstract: Methods for supplying deficiency of a key in a set of keys stored in devices includes receiving information (key values) on the keys from each device. Each key is assigned to a node or pair of nodes in a tree structure(s). If a position of a key in the tree structure in a first set of keys is stored in a first device with its value and corresponds to a position of a key in the tree structure in a second set of keys stored in a second device with its value, the first device and the second device are grouped together. Where there is a missing key in the first set of keys, a key corresponding to the missing key from the second set of keys is found, or a key common in the first set of keys and the second set of keys is found.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kohichi Kamijoh, Seiji Munetoh
  • Patent number: 10291404
    Abstract: Methods for supplying deficiency of a key in a set of keys stored in devices includes receiving information (key values) on the keys from each device. Each key is assigned to a node or pair of nodes in a tree structure(s). If a position of a key in the tree structure in a first set of keys is stored in a first device with its value and corresponds to a position of a key in the tree structure in a second set of keys stored in a second device with its value, the first device and the second device are grouped together. Where there is a missing key in the first set of keys, a key corresponding to the missing key from the second set of keys is found, or a key common in the first set of keys and the second set of keys is found.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kohichi Kamijoh, Seiji Munetoh
  • Publication number: 20190139840
    Abstract: A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Akihiro Horibe, Yasuteru Kohda, Seiji Munetoh, Chitra Subramanian, Kuniaki Sueoka
  • Publication number: 20190103328
    Abstract: A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.
    Type: Application
    Filed: October 27, 2017
    Publication date: April 4, 2019
    Inventors: Akihiro Horibe, Yasuteru Kohda, Seiji Munetoh, Chitra Subramanian, Kuniaki Sueoka
  • Publication number: 20190103327
    Abstract: A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.
    Type: Application
    Filed: October 2, 2017
    Publication date: April 4, 2019
    Inventors: Akihiro Horibe, Yasuteru Kohda, Seiji Munetoh, Chitra Subramanian, Kuniaki Sueoka
  • Patent number: 10216672
    Abstract: Described is a computer-implemented method for preventing time out during data transfer to an input/output device. Dummy data is generated and transferred to the input/output device at a time during data transfer, such as when a time out event may occur that would end the data transfer. The transfer of dummy data prevents a time out event from occurring.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Nobuyuki Ohba, Seiji Munetoh
  • Publication number: 20180262332
    Abstract: Methods for supplying deficiency of a key in a set of keys stored in devices includes receiving information (key values) on the keys from each device. Each key is assigned to a node or pair of nodes in a tree structure(s). If a position of a key in the tree structure in a first set of keys is stored in a first device with its value and corresponds to a position of a key in the tree structure in a second set of keys stored in a second device with its value, the first device and the second device are grouped together. Where there is a missing key in the first set of keys, a key corresponding to the missing key from the second set of keys is found, or a key common in the first set of keys and the second set of keys is found.
    Type: Application
    Filed: March 8, 2017
    Publication date: September 13, 2018
    Inventors: Kohichi Kamijoh, Seiji Munetoh
  • Publication number: 20180262333
    Abstract: Methods for supplying deficiency of a key in a set of keys stored in devices includes receiving information (key values) on the keys from each device. Each key is assigned to a node or pair of nodes in a tree structure(s). If a position of a key in the tree structure in a first set of keys is stored in a first device with its value and corresponds to a position of a key in the tree structure in a second set of keys stored in a second device with its value, the first device and the second device are grouped together. Where there is a missing key in the first set of keys, a key corresponding to the missing key from the second set of keys is found, or a key common in the first set of keys and the second set of keys is found.
    Type: Application
    Filed: October 31, 2017
    Publication date: September 13, 2018
    Inventors: Kohichi Kamijoh, Seiji Munetoh
  • Publication number: 20180181774
    Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 28, 2018
    Inventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff
  • Publication number: 20180075261
    Abstract: A computer implemented method for managing a content processed by a device includes: enabling a first content to be written to the device, the first content having been obtained using a first encrypted content and a device key in the device, the first encrypted content having been obtained using the first content and the device key outside the device, the device key being unique to the device and set in the device. The method further enables a second content to be read from the device, the second content having been obtained using a second encrypted content and the device key outside the device, the second encrypted content having been obtained using the second content and the device key in the device, the second content having been obtained using the first content in the device.
    Type: Application
    Filed: September 13, 2016
    Publication date: March 15, 2018
    Inventors: Kohichi Kamijoh, Seiji Munetoh
  • Patent number: 9891854
    Abstract: A method for managing main memory including DRAM and NVRAM in a computer depending on the operation state of the computer is provided. The method includes: (a) upon start of the computer, loading a program and the like into the DRAM, and loading predetermined read-only data and the like into the NVRAM; (b) in a state transition from a normal operation to a suspend state, moving data in the DRAM to the NVRAM; (c) in a state transition from the suspend state to the normal operation, reading data from the NVRAM for program execution; (d) in the case where a data write to the NVRAM occurs, stopping the data write, and moving data in a data area of the NVRAM subjected to the data write, to the DRAM; and (e) performing the data write to the DRAM to which the data has been moved.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Seiji Munetoh, Nobuyuki Ohba
  • Publication number: 20170262634
    Abstract: Analysis system, analysis method and program. The system includes: trace means for acquiring a command issued by software executed in an information processing system and a physical address of a memory used by the command as trace data, and recording the trace data to storage means; event detecting means for detecting an event caused to occur by the software and acquiring event information; conversion means for converting the event information to a memory access pattern configured with a plurality of commands for accessing the memory and a plurality of physical addresses; and memory accessing means for accessing the memory using the converted memory access pattern, causing the trace means to acquire trace data and record the trace data to the storage means.
    Type: Application
    Filed: May 30, 2017
    Publication date: September 14, 2017
    Inventor: Seiji Munetoh
  • Patent number: 9710351
    Abstract: Analysis system, analysis method and program. The system includes: trace means for acquiring a command issued by software executed in an information processing system and a physical address of a memory used by the command as trace data, and recording the trace data to storage means; event detecting means for detecting an event caused to occur by the software and acquiring event information; conversion means for converting the event information to a memory access pattern configured with a plurality of commands for accessing the memory and a plurality of physical addresses; and memory accessing means for accessing the memory using the converted memory access pattern, causing the trace means to acquire trace data and record the trace data to the storage means.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: July 18, 2017
    Assignee: International Business Machines Corporation
    Inventor: Seiji Munetoh
  • Publication number: 20170192697
    Abstract: A system and method of avoiding loss of memory trace data, including monitoring a first-in-first-out (FIFO) buffer to determine if the FIFO buffer has overflowed due to memory access, determining whether an overflow of the FIFO buffer is acceptable, changing an operating mode of a target system if overflow of the FIFO buffer is unacceptable to avoid FIFO buffer overflow, and collecting memory trace data on the memory accesses.
    Type: Application
    Filed: December 30, 2015
    Publication date: July 6, 2017
    Inventors: Seiji Munetoh, Nobuyuki Ohba
  • Publication number: 20170185551
    Abstract: Described is a computer-implemented method for preventing time out during data transfer to an input/output device. Dummy data is generated and transferred to the input/output device at a time during data transfer, such as when a time out event may occur that would end the data transfer. The transfer of dummy data prevents a time out event from occurring.
    Type: Application
    Filed: December 29, 2015
    Publication date: June 29, 2017
    Inventors: Nobuyuki Ohba, Seiji Munetoh
  • Patent number: 9632725
    Abstract: An improved method for identifying trace data relating to a particular virtual machine from trace data acquired by a tracer node. The method is executed in a computing environment including at least one processing node and a tracer node for acquiring a trace of access to a memory apparatus thereof. The method includes the steps of: starting recording of trace data containing information of the trace of the access to the memory apparatus of the tracer node; storing, in response to migration of the particular virtual machine from a given processing node to the tracer node, information identifying a physical address of the memory apparatus of the tracer node, the physical address being assigned to the particular virtual machine; and identifying the trace data relating to the particular virtual machine from the trace data, using the assigned physical address of the memory apparatus of the tracer node.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: April 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Seiji Munetoh
  • Patent number: 9606890
    Abstract: Analysis system, analysis method and program. The system includes: trace means for acquiring a command issued by software executed in an information processing system and a physical address of a memory used by the command as trace data, and recording the trace data to storage means; event detecting means for detecting an event caused to occur by the software and acquiring event information; conversion means for converting the event information to a memory access pattern configured with a plurality of commands for accessing the memory and a plurality of physical addresses; and memory accessing means for accessing the memory using the converted memory access pattern, causing the trace means to acquire trace data and record the trace data to the storage means.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventor: Seiji Munetoh
  • Publication number: 20170075618
    Abstract: A method for managing main memory including DRAM and NVRAM in a computer depending on the operation state of the computer is provided. The method includes: (a) upon start of the computer, loading a program and the like into the DRAM, and loading predetermined read-only data and the like into the NVRAM; (b) in a state transition from a normal operation to a suspend state, moving data in the DRAM to the NVRAM; (c) in a state transition from the suspend state to the normal operation, reading data from the NVRAM for program execution; (d) in the case where a data write to the NVRAM occurs, stopping the data write, and moving data in a data area of the NVRAM subjected to the data write, to the DRAM; and (e) performing the data write to the DRAM to which the data has been moved.
    Type: Application
    Filed: November 11, 2016
    Publication date: March 16, 2017
    Applicant: International Business Machines Corporation
    Inventors: Seiji Munetoh, Nobuyuki Ohba
  • Patent number: 9571513
    Abstract: A monitoring device configured to monitor a network to which plural controllers are connected which includes a decoder configured to extract target data belonging to a target data group from data received from the plural controllers, a first comparator configured to determine whether an immutable part of the target data is known or anomalous, a second comparator configured to determine whether a reception interval of the target data group is normal or anomalous, a third comparator configured to determine whether the number of the target data having been received and included in the target data group is normal or anomalous, and determine whether each reception interval between the target data is normal or anomalous, and a warning counter configured to individually count the number of anomalies determined by the first comparator, the number of anomalies determined by the second comparator, and the number of anomalies determined by the third comparator.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Seiji Munetoh
  • Publication number: 20170026397
    Abstract: A monitoring device configured to monitor a network to which plural controllers are connected which includes a decoder configured to extract target data belonging to a target data group from data received from the plural controllers, a first comparator configured to determine whether an immutable part of the target data is known or anomalous, a second comparator configured to determine whether a reception interval of the target data group is normal or anomalous, a third comparator configured to determine whether the number of the target data having been received and included in the target data group is normal or anomalous, and determine whether each reception interval between the target data is normal or anomalous, and a warning counter configured to individually count the number of anomalies determined by the first comparator, the number of anomalies determined by the second comparator, and the number of anomalies determined by the third comparator.
    Type: Application
    Filed: September 6, 2016
    Publication date: January 26, 2017
    Inventor: SEIJI MUNETOH