Patents by Inventor Seiji Munetoh
Seiji Munetoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240079326Abstract: An IC memory device includes a substrate and an array of memory cells on the substrate. Each memory cell includes at least one memory cell transistor in a layer of the device adjacent to the substrate. In the same layer, the device also includes a plurality of shunt transistors. The device also includes a buried metal signal rail, which is disposed between the array of memory cells and the plurality of shunt transistors in a buried layer that is embedded into the substrate below the transistors. The device also includes single-layer vias, which are in same layer as the transistors and electrically connect the memory cell transistors to the shunt transistors through the buried metal signal rail.Type: ApplicationFiled: September 6, 2022Publication date: March 7, 2024Inventors: Biswanath Senapati, SEIJI MUNETOH, Nicholas Anthony Lanzillo, Lawrence A. Clevenger, Geoffrey Burr, Kohji Hosokawa
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Publication number: 20230187314Abstract: A memory cell in a backside of a wafer and methods of forming the memory cell are described. A buried metal structure can be formed through a frontside of a substrate. At least one device can be formed on the frontside of a substrate, where the at least one device can be connected to the buried metal structure in the substrate. A through silicon via (TSV) can be formed through a backside of the substrate, where the TSV can be connected to the buried metal structure. A memory cell can be formed on the backside of the substrate, where the memory cell can be connected to the TSV.Type: ApplicationFiled: December 15, 2021Publication date: June 15, 2023Inventors: Biswanath Senapati, Seiji Munetoh, Nicholas Anthony Lanzillo, Lawrence A. Clevenger, Geoffrey Burr, Kohji Hosokawa
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Patent number: 11411739Abstract: A processor-implemented method imposes trust at the edge of a blockchain. A hardware interrogator in a terminal interrogates an Internet of Things Smart Device (IoTSD). The IoTSD is an off-line device that is associated with a physical product. The IoTSD includes a cryptographic processor and one or more state sensors that monitor a state of the physical product. The hardware interrogator detects an event that is described by an encrypted entry in the IoTSD. The terminal transmits, to a blockchain, a transaction that describes the event that is detected by the hardware interrogator, such that the blockchain adds the transaction to a blockchain that is dedicated to the physical product, and the blockchain establishes a state of the physical product.Type: GrantFiled: February 7, 2019Date of Patent: August 9, 2022Assignee: Internatiional Business Machines CorporationInventors: Frank R. Libsch, Seiji Munetoh, Abhilash Narendra, Ghavam G. Shahidi
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Patent number: 11216595Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.Type: GrantFiled: September 21, 2019Date of Patent: January 4, 2022Assignee: International Business Machines CorporationInventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff
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Patent number: 11190362Abstract: Devices, computer-implemented methods, and systems that can facilitate radio frequency identification components are provided. According to an embodiment, a device can comprise a memory that can be coupled to an integrated circuit device that can have a processor and an accelerator component that can execute a cryptographic module. The device can further comprise a radio frequency identification device that can be coupled to the integrated circuit device that can communicate with a radio frequency identification reader device based on the cryptographic module.Type: GrantFiled: January 3, 2019Date of Patent: November 30, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chitra Subramanian, Seiji Munetoh, Frank Robert Libsch, Daniel Joseph Friedman, Ghavam G. Shahidi, Arun Paidimarri
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Patent number: 11122070Abstract: A monitoring device configured to monitor a network to which plural controllers are connected which includes a decoder configured to extract target data belonging to a target data group from data received from the plural controllers, a first comparator configured to determine whether an immutable part of the target data is known or anomalous, a second comparator configured to determine whether a reception interval of the target data group is normal or anomalous, a third comparator configured to determine whether the number of the target data having been received and included in the target data group is normal or anomalous, and determine whether each reception interval between the target data is normal or anomalous, and a warning counter configured to individually count the number of anomalies determined by the first comparator, the number of anomalies determined by the second comparator, and the number of anomalies determined by the third comparator.Type: GrantFiled: December 11, 2019Date of Patent: September 14, 2021Assignee: International Business Machines CorporationInventor: Seiji Munetoh
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Patent number: 11093429Abstract: An apparatus for data transfer includes a first node connected to a bus to communicate bidirectionally, and second nodes connected in series to the bus. Each second node lacks an internal clock and has fixed pads including a power, a ground, and signal pads to transfer a data frame, return data pads for a return signal, select pads for a selection signal and clock pads for a clock signal. Each second node is indexed by a hop count in the frame that is incremented each time the frame is transferred in topological order. Each second node is selectable using a mode defined by a combination of the hop count, a mask field and an address field in the frame. The signal pads are used for frame transfer in a selected mode controlled by a combination of the selection, clock and return signals.Type: GrantFiled: January 30, 2020Date of Patent: August 17, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Seiji Munetoh
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Publication number: 20210240652Abstract: An apparatus for data transfer includes a first node connected to a bus to communicate bidirectionally, and second nodes connected in series to the bus. Each second node lacks an internal clock and has fixed pads including a power, a ground, and signal pads to transfer a data frame, return data pads for a return signal, select pads for a selection signal and clock pads for a clock signal. Each second node is indexed by a hop count in the frame that is incremented each time the frame is transferred in topological order. Each second node is selectable using a mode defined by a combination of the hop count, a mask field and an address field in the frame. The signal pads are used for frame transfer in a selected mode controlled by a combination of the selection, clock and return signals.Type: ApplicationFiled: January 30, 2020Publication date: August 5, 2021Inventor: Seiji Munetoh
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Patent number: 10997321Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.Type: GrantFiled: September 21, 2019Date of Patent: May 4, 2021Assignee: International Business Machines CorporationInventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff
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Patent number: 10963364Abstract: Analysis system, analysis method and program. The system includes: trace means for acquiring a command issued by software executed in an information processing system and a physical address of a memory used by the command as trace data, and recording the trace data to storage means; event detecting means for detecting an event caused to occur by the software and acquiring event information; conversion means for converting the event information to a memory access pattern configured with a plurality of commands for accessing the memory and a plurality of physical addresses; and memory accessing means for accessing the memory using the converted memory access pattern, causing the trace means to acquire trace data and record the trace data to the storage means.Type: GrantFiled: June 4, 2019Date of Patent: March 30, 2021Assignee: International Business Machines CorporationInventor: Seiji Munetoh
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Patent number: 10937484Abstract: A system and method of avoiding loss of memory trace data, including monitoring a first-in-first-out (FIFO) buffer to determine if the FIFO buffer has overflowed due to memory access, determining whether an overflow of the FIFO buffer is acceptable, changing an operating mode of a target system if overflow of the FIFO buffer is unacceptable to avoid FIFO buffer overflow, and collecting memory trace data on the memory accesses.Type: GrantFiled: December 30, 2015Date of Patent: March 2, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Seiji Munetoh, Nobuyuki Ohba
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Patent number: 10884918Abstract: A semiconductor structure includes a first processor on a first die of a substrate. There is a second processor on a second die of the substrate. There is a one-time programmable (OTP) memory programming circuit, outside of the first and second die, and shared by the first and second processors. Each of the first and second processors include a one-time programmable (OTP) memory. The OTP memory programming circuit is configured to program each OTP memory.Type: GrantFiled: January 28, 2019Date of Patent: January 5, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chitra Subramanian, Seiji Munetoh, Ghavam Shahidi
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Publication number: 20200259658Abstract: A processor-implemented method imposes trust at the edge of a blockchain. A hardware interrogator in a terminal interrogates an Internet of Things Smart Device (IoTSD). The IoTSD is an off-line device that is associated with a physical product. The IoTSD includes a cryptographic processor and one or more state sensors that monitor a state of the physical product. The hardware interrogator detects an event that is described by an encrypted entry in the IoTSD. The terminal transmits, to a blockchain, a transaction that describes the event that is detected by the hardware interrogator, such that the blockchain adds the transaction to a blockchain that is dedicated to the physical product, and the blockchain establishes a state of the physical product.Type: ApplicationFiled: February 7, 2019Publication date: August 13, 2020Inventors: FRANK R. LIBSCH, SEIJI MUNETOH, ABHILASH NARENDRA, GHAVAM G. SHAHIDI
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Publication number: 20200242022Abstract: A semiconductor structure includes a first processor on a first die of a substrate. There is a second processor on a second die of the substrate. There is a one-time programmable (OTP) memory programming circuit, outside of the first and second die, and shared by the first and second processors. Each of the first and second processors include a one-time programmable (OTP) memory. The OTP memory programming circuit is configured to program each OTP memory.Type: ApplicationFiled: January 28, 2019Publication date: July 30, 2020Inventors: Chitra Subramanian, Seiji Munetoh, Ghavam Shahidi
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Publication number: 20200220736Abstract: Devices, computer-implemented methods, and systems that can facilitate radio frequency identification components are provided. According to an embodiment, a device can comprise a memory that can be coupled to an integrated circuit device that can have a processor and an accelerator component that can execute a cryptographic module. The device can further comprise a radio frequency identification device that can be coupled to the integrated circuit device that can communicate with a radio frequency identification reader device based on the cryptographic module.Type: ApplicationFiled: January 3, 2019Publication date: July 9, 2020Inventors: Chitra Subramanian, Seiji Munetoh, Frank Robert Libsch, Daniel Joseph Friedman, Ghavam G. Shahidi, Arun Paidimarri
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Patent number: 10679912Abstract: A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.Type: GrantFiled: October 2, 2017Date of Patent: June 9, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Akihiro Horibe, Yasuteru Kohda, Seiji Munetoh, Chitra Subramanian, Kuniaki Sueoka
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Publication number: 20200120125Abstract: A monitoring device configured to monitor a network to which plural controllers are connected which includes a decoder configured to extract target data belonging to a target data group from data received from the plural controllers, a first comparator configured to determine whether an immutable part of the target data is known or anomalous, a second comparator configured to determine whether a reception interval of the target data group is normal or anomalous, a third comparator configured to determine whether the number of the target data having been received and included in the target data group is normal or anomalous, and determine whether each reception interval between the target data is normal or anomalous, and a warning counter configured to individually count the number of anomalies determined by the first comparator, the number of anomalies determined by the second comparator, and the number of anomalies determined by the third comparator.Type: ApplicationFiled: December 11, 2019Publication date: April 16, 2020Inventor: SEIJI MUNETOH
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Patent number: 10560470Abstract: A monitoring device configured to monitor a network to which plural controllers are connected which includes a decoder configured to extract target data belonging to a target data group from data received from the plural controllers, a first comparator configured to determine whether an immutable part of the target data is known or anomalous, a second comparator configured to determine whether a reception interval of the target data group is normal or anomalous, a third comparator configured to determine whether the number of the target data having been received and included in the target data group is normal or anomalous, and determine whether each reception interval between the target data is normal or anomalous, and a warning counter configured to individually count the number of anomalies determined by the first comparator, the number of anomalies determined by the second comparator, and the number of anomalies determined by the third comparator.Type: GrantFiled: September 6, 2016Date of Patent: February 11, 2020Assignee: International Business Machines CorporationInventor: Seiji Munetoh
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Publication number: 20200019731Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.Type: ApplicationFiled: September 21, 2019Publication date: January 16, 2020Inventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff
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Publication number: 20200019732Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.Type: ApplicationFiled: September 21, 2019Publication date: January 16, 2020Inventors: Richard H. Boivie, Eduard A. Cartier, Daniel J. Friedman, Kohji Hosokawa, Charanjit Jutla, Wanki Kim, Chandrasekara Kothandaraman, Chung Lam, Frank R. Libsch, Seiji Munetoh, Ramachandran Muralidhar, Vijay Narayanan, Dirk Pfeiffer, Devendra K. Sadana, Ghavam G. Shahidi, Robert L. Wisnieff