Patents by Inventor Seiki Sakuyama
Seiki Sakuyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7879713Abstract: A mounting method of a semiconductor element whereby the semiconductor element is mounted on a wiring board via an outside connection projection electrode not containing lead (Pb), the mounting method includes a step of applying a reflow heating process for connecting the outside connection projection electrode of the semiconductor element and the wiring board and then cooling the connected semiconductor element and wiring board at a cooling rate equal to and lower than 0.5° C./s.Type: GrantFiled: January 17, 2007Date of Patent: February 1, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Joji Fujimori, Seiki Sakuyama, Toshiya Akamatsu
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Publication number: 20100315796Abstract: A conductive material includes a first metal part whose main ingredient is a first metal; a second metal part formed on the first metal part and whose main ingredient is a second metal, the second metal having a melting point lower than a melting point of the first metal, which second metal can form a metallic compound with the first metal; and a third metal part whose main ingredient is a third metal, which third metal can make a eutectic reaction with the second metal.Type: ApplicationFiled: August 5, 2010Publication date: December 16, 2010Applicant: FUJITSU LIMITEDInventors: Seiki Sakuyama, Taiji Sakai
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Publication number: 20100270362Abstract: A composition for controlling a temperature elevation of an electronic component when soldering the electronic component on a substrate, includes a first resin for providing the composition with adhesion to the electronic component, a curing agent for curing the first resin by heat treatment for soldering, and a second resin for facilitating removal of the composition from the electronic component.Type: ApplicationFiled: July 6, 2010Publication date: October 28, 2010Applicant: FUJITSU LIMITEDInventor: Seiki Sakuyama
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Publication number: 20100218853Abstract: The method for bonding a semiconductor element comprises the step of applying to solder bumps 10 of a semiconductor chip 12 a soldering flux 16 which contains a thermosetting resin, a polyhydric alcohol and an organic acid and in which the thermosetting resin remains uncured after reflow-bonding, the step of reflow-bonding the solder bumps 10 to the electrodes 18 of the circuit board 20 with the soldering flux 16 while melting the solder bumps 10, and the step of filling an underfill material 22 between the semiconductor chip 12 and the circuit board 20 with the soldering flux 16 being left, the underfill material 22 containing a thermosetting resin of the same group as the thermosetting resin contained in the soldering flux 16 and at least one of a curing agent and a cure catalyst for curing the thermosetting resins.Type: ApplicationFiled: May 17, 2010Publication date: September 2, 2010Applicant: FUJITSU LIMITEDInventors: Toshiya AKAMATSU, Seiki SAKUYAMA
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Publication number: 20100170804Abstract: Tin plating film composed of tin or tin alloy is formed on a front surface and a rear surface of a substrate composing a lead frame. As tin alloy, for example, tin-copper alloy (content of copper: 2 mass %), tin-bismuth alloy (content of bismuth: 2 mass %) and the like can be cited. The substrate is composed of, for example, Cu alloy or the like. Within the tin plating film, plural crystal grains are arranged irregularly. Further, plural gap portions exist within the tin plating film. An external stress is reduced even if a bending process or the like are performed subsequently, because the gap portions exist within the tin plating film. Consequently, growths of whiskers accompanied by the external stress are suppressed.Type: ApplicationFiled: March 15, 2010Publication date: July 8, 2010Applicant: FUJITSU LIMITEDInventor: Seiki Sakuyama
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Patent number: 7743966Abstract: The method for bonding a semiconductor element comprises the step of applying to solder bumps 10 of a semiconductor chip 12 a soldering flux 16 which contains a thermosetting resin, a polyhydric alcohol and an organic acid and in which the thermosetting resin remains uncured after reflow-bonding, the step of reflow-bonding the solder bumps 10 to the electrodes 18 of the circuit board 20 with the soldering flux 16 while melting the solder bumps 10, and the step of filling an underfill material 22 between the semiconductor chip 12 and the circuit board 20 with the soldering flux 16 being left, the underfill material 22 containing a thermosetting resin of the same group as the thermosetting resin contained in the soldering flux 16 and at least one of a curing agent and a cure catalyst for curing the thermosetting resins.Type: GrantFiled: June 27, 2006Date of Patent: June 29, 2010Assignee: Fujitsu LimitedInventors: Toshiya Akamatsu, Seiki Sakuyama
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Publication number: 20100089982Abstract: A member having a coating film capable of suppressing whisker generation is provided. The coating film (3) including a plurality of crystalline grains (3a) made of tin or tin alloy is formed above the surface of the base member (1). An intermetallic compound (3b) of tin and the first metal is being formed along the crystalline grain boundaries of the coating film.Type: ApplicationFiled: June 17, 2005Publication date: April 15, 2010Applicant: FUJITSU LIMITEDInventor: Seiki Sakuyama
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Publication number: 20090090543Abstract: There is provided a circuit board to which a solder ball composed of a lead (Pb)-free solder is to be connected, a semiconductor device including an electrode and a solder ball composed of a lead (Pb)-free solder disposed on the electrode, and a method of manufacturing the semiconductor device, in which mounting reliability can be improved by enhancing the bonding strength (adhesion strength) between the solder ball composed of a lead (Pb)-free solder and the electrode.Type: ApplicationFiled: October 1, 2008Publication date: April 9, 2009Applicant: FUJITSU LIMITEDInventors: Masaharu FURUYAMA, Daisuke MIZUTANI, Seiki SAKUYAMA, Toshiya AKAMATSU
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Publication number: 20080124834Abstract: A mounting method of a semiconductor element whereby the semiconductor element is mounted on a wiring board via an outside connection projection electrode not containing lead (Pb), the mounting method includes a step of applying a reflow heating process for connecting the outside connection projection electrode of the semiconductor element and the wiring board and then cooling the connected semiconductor element and wiring board at a cooling rate equal to and lower than 0.5° C./s.Type: ApplicationFiled: January 17, 2007Publication date: May 29, 2008Applicant: FUJITSU LIMITEDInventors: Joji Fujimori, Seiki Sakuyama, Toshiya Akamatsu
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Publication number: 20070221710Abstract: The method for bonding a semiconductor element comprises the step of applying to solder bumps 10 of a semiconductor chip 12 a soldering flux 16 which contains a thermosetting resin, a polyhydric alcohol and an organic acid and in which the thermosetting resin remains uncured after reflow-bonding, the step of reflow-bonding the solder bumps 10 to the electrodes 18 of the circuit board 20 with the soldering flux 16 while melting the solder bumps 10, and the step of filling an underfill material 22 between the semiconductor chip 12 and the circuit board 20 with the soldering flux 16 being left, the underfill material 22 containing a thermosetting resin of the same group as the thermosetting resin contained in the soldering flux 16 and at least one of a curing agent and a cure catalyst for curing the thermosetting resins.Type: ApplicationFiled: June 27, 2006Publication date: September 27, 2007Applicant: FUJITSU LIMITEDInventors: Toshiya Akamatsu, Seiki Sakuyama
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Publication number: 20070224444Abstract: Tin plating film composed of tin or tin alloy is formed on a front surface and a rear surface of a substrate composing a lead frame. As tin alloy, for example, tin-copper alloy (content of copper: 2 mass %), tin-bismuth alloy (content of bismuth: 2 mass %) and the like can be cited. The substrate is composed of, for example, Cu alloy or the like. Within the tin plating film, plural crystal grains are arranged irregularly. Further, plural gap portions exist within the tin plating film. An external stress is reduced even if a bending process or the like are performed subsequently, because the gap portions exist within the tin plating film. Consequently, growths of whiskers accompanied by the external stress are suppressed.Type: ApplicationFiled: June 27, 2006Publication date: September 27, 2007Applicant: FUJITSU LIMITEDInventor: Seiki Sakuyama
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Publication number: 20070218312Abstract: A plated structure is disclosed that includes a base formed of a copper-based material containing copper as a major component, a plating film formed of a tin-based material containing tin as a major component and provided over the base, and a tin-copper compound barrier film located at the boundary between the base and the plating film. The density of the tin-copper compound barrier film is greater than that of copper.Type: ApplicationFiled: June 23, 2006Publication date: September 20, 2007Applicant: FUJITSU LIMITEDInventors: Seiki Sakuyama, Kozo Shimizu
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Patent number: 7189927Abstract: An electronic component with bump electrodes includes a surface-protecting insulating film of adequate thickness and bump elements of adequate height, and allows the occurrence of open defects in the manufacturing process to be appropriately reduced. An electronic component with bump electrodes (X1) includes a substrate (11), electrode pads (12) provided on the substrate (11), an insulating film (13) that has openings (13a) in correspondence with the electrode pads (12) and is laminated and formed on the substrate (11), electroconductive connecting elements (14) provided on the electrode pads (12) in the openings (13a), and bump elements (15) that are in direct contact with the electroconductive connecting elements (14) and project from the openings (13a).Type: GrantFiled: May 9, 2003Date of Patent: March 13, 2007Assignee: Fujitsu LimitedInventor: Seiki Sakuyama
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Patent number: 7119000Abstract: The resist film is provided on the surface of the substrate having electrodes, and openings are provided in the resist film at positions of the electrodes on the substrate. The first metal is supplied into the openings. The first metal is then heated to melt and coagulate it. The second metal is then supplied into the openings on the first metal. The first metal and the second metal are heated to melt and coagulate them. The resist film is finally removed. By this method, excellent solder bumps can be formed on the substrate without remnants of the resist film being left on the substrate.Type: GrantFiled: February 5, 2004Date of Patent: October 10, 2006Assignee: Fujitsu LimitedInventors: Kozo Shimizu, Seiki Sakuyama
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Patent number: 6873056Abstract: A process of making an electrode-to-electrode bond structure includes a step of forming a resin coating on a first bonding object having a first electrode portion in a manner such that the resin coating covers the first electrode portion. Then, an opening is formed in the resin coating to expose the first electrode portion. Then, the opening is filled with a metal paste containing a metal and a resin component. Then, the first bonding object is placed on a second bonding object having a second electrode portion in a manner such that the metal paste filled in the opening faces the second electrode portion while the resin coating contacts the second bonding object. Finally, heat-treatment is performed to cause the first electrode portion and the second electrode portion to be electrically connected with each other via the metal while causing the resin coating to harden.Type: GrantFiled: November 12, 2003Date of Patent: March 29, 2005Assignee: Fujitsu LimitedInventors: Seiki Sakuyama, Nobuhiro Imaizumi, Tomohisa Yagi
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Publication number: 20040180527Abstract: The resist film is provided on the surface of the substrate having electrodes, and openings are provided in the resist film at positions of the electrodes on the substrate. The first metal is supplied into the openings. The first metal is then heated to melt and coagulate it. The second metal is then supplied into the openings on the first metal. The first metal and the second metal are heated to melt and coagulate them. The resist film is finally removed. By this method, excellent solder bumps can be formed on the substrate without remnants of the resist film being left on the substrate.Type: ApplicationFiled: February 5, 2004Publication date: September 16, 2004Applicant: FUJITSU LIMITEDInventors: Kozo Shimizu, Seiki Sakuyama
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Publication number: 20040106232Abstract: A process of making an electrode-to-electrode bond structure includes a step of forming a resin coating on a first bonding object having a first electrode portion in a manner such that the resin coating covers the first electrode portion. Then, an opening is formed in the resin coating to expose the first electrode portion. Then, the opening is filled with a metal paste containing a metal and a resin component. Then, the first bonding object is placed on a second bonding object having a second electrode portion in a manner such that the metal paste filled in the opening faces the second electrode portion while the resin coating contacts the second bonding object. Finally, heat-treatment is performed to cause the first electrode portion and the second electrode portion to be electrically connected with each other via the metal while causing the resin coating to harden.Type: ApplicationFiled: November 12, 2003Publication date: June 3, 2004Applicant: FUJITSU LIMITEDInventors: Seiki Sakuyama, Nobuhiro Imaizumi, Tomohisa Yagi
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Patent number: 6689639Abstract: A method of making a semiconductor device includes a resin film forming step for forming a resin film on a semiconductor substrate 10 provided with electrode portions 11 to cover the electrode portions 11, an opening forming step for forming openings in the resin film at locations corresponding to the electrode portions 11, a loading step for loading a bump material in the openings, a bump forming step for forming bumps 41 in the openings by heating, and a removing step for removing the resin film.Type: GrantFiled: November 12, 2002Date of Patent: February 10, 2004Assignee: Fujitsu LimitedInventors: Seiki Sakuyama, Masayuki Ochiai, Ichiro Yamaguchi, Joji Fujimori
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Patent number: 6670264Abstract: A process of making an electrode-to-electrode bond structure includes a step of forming a resin coating on a first bonding object having a first electrode portion in a manner such that the resin coating covers the first electrode portion. Then, an opening is formed in the resin coating to expose the first electrode portion. Then, the opening is filled with a metal paste containing a metal and a resin component. Then, the first bonding object is placed on a second bonding object having a second electrode portion in a manner such that the metal paste filled in the opening faces the second electrode portion while the resin coating contacts the second bonding object. Finally, heat-treatment is performed to cause the first electrode portion and the second electrode portion to be electrically connected with each other via the metal while causing the resin coating to harden.Type: GrantFiled: April 18, 2002Date of Patent: December 30, 2003Assignee: Fujitsu LimitedInventors: Seiki Sakuyama, Nobuhiro Imaizumi, Tomohisa Yagi
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Publication number: 20030214795Abstract: An electronic component with bump electrodes includes a surface-protecting insulating film of adequate thickness and bump elements of adequate height, and allows the occurrence of open defects in the manufacturing process to be appropriately reduced. An electronic component with bump electrodes (X1) includes a substrate (11), electrode pads (12) provided on the substrate (11), an insulating film (13) that has openings (13a) in correspondence with the electrode pads (12) and is laminated and formed on the substrate (11), electroconductive connecting elements (14) provided on the electrode pads (12) in the openings (13a), and bump elements (15) that are in direct contact with the electroconductive connecting elements (14) and project from the openings (13a).Type: ApplicationFiled: May 9, 2003Publication date: November 20, 2003Applicant: FUJITSU LIMITEDInventor: Seiki Sakuyama