Patents by Inventor Seizo Kakimoto
Seizo Kakimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7879704Abstract: A memory function body has a medium interposed between a first conductor (e.g., a conductive substrate) and a second conductor (e.g., an electrode) and consisting of a first material (e.g., silicon oxide or silicon nitride). The medium contains particles. Each particle is covered with a second material (e.g., silver oxide) and formed of a third material (e.g., silver). The second material functions as a barrier against passage of electric charges, and the third material has a function of retaining electric charges. The third material is introduced into the medium by, for example, a negative ion implantation method.Type: GrantFiled: February 13, 2007Date of Patent: February 1, 2011Assignee: Sharp Kabushiki KaishaInventors: Nobutoshi Arai, Hiroshi Iwata, Seizo Kakimoto
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Patent number: 7851777Abstract: A resistance-changing function body includes an object made of a first substance and interposed between a first electrode and a second electrode, and a plurality of particles made of a second substance and arranged within the object so that an electrical resistance between the first electrode and the second electrode is changed before and after application of a specified voltage to between the first electrode and the second electrode. The first substance makes an electrical barrier against the second substance. With this constitution, by applying a specified voltage to between the first electrode and the second electrode, the electrical resistance can be changed depending on a state of the particles made of the second substance. Also, by virtue of a simple structure, a resistance-changing function body of small size is provided with low cost.Type: GrantFiled: November 14, 2008Date of Patent: December 14, 2010Assignee: Sharp Kabushiki KaishaInventors: Nobutoshi Arai, Hiroshi Iwata, Seizo Kakimoto
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Patent number: 7711012Abstract: The yield of a semiconductor device is improved which has a large-scale logic circuit or which has both a logic circuit and a memory. A basic circuit block is provided with an input/output circuit. A transmission line and a branch line connect the input/output circuits so that information can be exchanged through the input/output circuits between one basic circuit block and another basic circuit block. The memory in each basic circuit block or in each input/output circuit can be programmed from the outside to designate the destination of a signal. By thus changing the program in the memory, the transmission destination of a signal can be changed to give various functions efficiently with a limited circuit scale. Moreover, if a basic circuit block fails another basic circuit block substitutes for it to improve the yield drastically.Type: GrantFiled: February 13, 2002Date of Patent: May 4, 2010Assignee: Sharp Kabushiki KaishaInventors: Hiroshi Iwata, Tomohisa Okuno, Akihide Shibata, Seizo Kakimoto
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Publication number: 20090085025Abstract: A resistance-changing function body includes an object made of a first substance and interposed between a first electrode and a second electrode, and a plurality of particles made of a second substance and arranged within the object so that an electrical resistance between the first electrode and the second electrode is changed before and after application of a specified voltage to between the first electrode and the second electrode. The first substance makes an electrical barrier against the second substance. With this constitution, by applying a specified voltage to between the first electrode and the second electrode, the electrical resistance can be changed depending on a state of the particles made of the second substance. Also, by virtue of a simple structure, a resistance-changing function body of small size is provided with low cost.Type: ApplicationFiled: November 14, 2008Publication date: April 2, 2009Inventors: Nobutoshi ARAI, Hiroshi Iwata, Seizo Kakimoto
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Patent number: 7462857Abstract: A resistance-changing function body includes an object made of a first substance and interposed between a first electrode and a second electrode, and a plurality of particles made of a second substance and arranged within the object so that an electrical resistance between the first electrode and the second electrode is changed before and after application of a specified voltage to between the first electrode and the second electrode. The first substance makes an electrical barrier against the second substance. With this constitution, by applying a specified voltage to between the first electrode and the second electrode, the electrical resistance can be changed depending on a state of the particles made of the second substance. Also, by virtue of a simple structure, a resistance-changing function body of small size is provided with low cost.Type: GrantFiled: September 18, 2003Date of Patent: December 9, 2008Assignee: Sharp Kabushiki KaishaInventors: Nobutoshi Arai, Hiroshi Iwata, Seizo Kakimoto
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Patent number: 7352024Abstract: There is provided a semiconductor storage device capable of high integration. On a top surface of a semiconductor substrate, a plurality of device isolation regions (16) each extending and meandering in a lateral direction are formed so as to be arrayed with respect to a longitudinal direction, by which active regions are defined between neighboring ones of the device isolation regions (16), respectively. Dopant diffusion regions (source or drain) are formed at individual turnover portions (corresponding to contacts (14), (15)), respectively, of the meanders within the active regions. A plurality of word lines (11) extending straight in the longitudinal direction run on the channel regions within the active regions via a film having memory function, respectively. A first bit line (12) extending straight in the lateral direction runs on the dopant diffusion region (corresponding to contact (14)) provided at a crest-side turnover portion.Type: GrantFiled: February 21, 2002Date of Patent: April 1, 2008Assignee: Sharp Kabushiki KaishaInventors: Hiroshi Iwata, Akihide Shibata, Seizo Kakimoto
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Patent number: 7187043Abstract: A memory function body has a medium interposed between a first conductor (e.g., a conductive substrate) and a second conductor (e.g., an electrode) and consisting of a first material (e.g., silicon oxide or silicon nitride). The medium contains particles. Each particle is covered with a second material (e.g., silver oxide) and formed of a third material (e.g., silver). The second material functions as a barrier against passage of electric charges, and the third material has a function of retaining electric charges. The third material is introduced into the medium by, for example, a negative ion implantation method.Type: GrantFiled: March 11, 2004Date of Patent: March 6, 2007Assignee: Sharp Kabushiki KaishaInventors: Nobutoshi Arai, Hiroshi Iwata, Seizo Kakimoto
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Patent number: 7176526Abstract: A semiconductor device 1910 comprises a semiconductor substrate 100 including an isolation region 101 and an active region 102, a gate electrode 104 provided on the active region 102 via a gate insulating film 103, part of a side of the gate electrode 104 being covered with a gate electrode side wall insulating film 105, and a source region 106 and a drain region 106 provided on opposite sides of the gate electrode 104 via the gate electrode side wall insulating film 105. At least one of the source region 106 and the drain region 106 has a second surface for contacting a contact conductor. The second surface is tilted with respect to a first surface A–A?. An angle between the second surface and a surface of the isolation region is 80 degrees or less.Type: GrantFiled: July 27, 2004Date of Patent: February 13, 2007Assignee: Sharp Kabushiki KaishaInventors: Hiroshi Iwata, Akihide Shibata, Seizo Kakimoto, Kouichiro Adachi, Masayuki Nakano
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Patent number: 7084465Abstract: There is provided a semiconductor device including DTMOS and a substrate variable-bias transistor and a portable electronic device both operable with reduced power consumption. N-type deep well regions are formed in one P-type semiconductor substrate. The N-type deep well regions are electrically isolated by the P-type semiconductor substrate. Over the N-type deep well regions, a P-type deep well region and a P-type shallow well region are formed to fabricate an N-type substrate variable-bias transistor. Over the N-type deep well region, an N-type shallow well region is formed to fabricate a P-type substrate variable-bias transistor. Further a P-type DTMOS and an N-type DTMOD are fabricated.Type: GrantFiled: December 26, 2001Date of Patent: August 1, 2006Assignee: Sharp Kabushiki KaishaInventors: Akihide Shibata, Hiroshi Iwata, Seizo Kakimoto
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Publication number: 20060154432Abstract: A resistance-changing function body includes an object made of a first substance and interposed between a first electrode and a second electrode, and a plurality of particles made of a second substance and arranged within the object so that an electrical resistance between the first electrode and the second electrode is changed before and after application of a specified voltage to between the first electrode and the second electrode. The first substance makes an electrical barrier against the second substance. With this constitution, by applying a specified voltage to between the first electrode and the second electrode, the electrical resistance can be changed depending on a state of the particles made of the second substance. Also, by virtue of a simple structure, a resistance-changing function body of small size is provided with low cost.Type: ApplicationFiled: September 18, 2003Publication date: July 13, 2006Applicant: Sharp Kabushiki KaishaInventors: Nobutoshi Arai, Hiroshi Iwata, Seizo Kakimoto
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Patent number: 7074676Abstract: A memory film operable at a low voltage and a method of manufacturing the memory film; the method, comprising the steps of forming a first insulation film (112) on a semiconductor substrate (111) forming a first electrode, forming a first conductor film (113) on the first insulation film (112), forming a second insulation film (112B) on the surface of the first conductor film (113), forming a third insulation film containing conductor particulates (114, 115) on the second insulation film (112B), and forming a second conductor film forming a second electrode on the third insulation film.Type: GrantFiled: February 13, 2002Date of Patent: July 11, 2006Assignees: Sharp Kabushiki KaishaInventors: Hiroshi Iwata, Akihide Shibata, Nobutoshi Arai, Takayuki Ogura, Kouichirou Adachi, Seizo Kakimoto, Yukio Yasuda, Shigeaki Zaima, Akira Sakai
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Patent number: 7030456Abstract: A memory function body 113, which includes a plurality of silver particles 103 covered with silver oxide 104, is interposed between a first electrode 300 and a second electrode 411. A magnitude of a current through the memory function body 113 changes on applying a prescribed voltage between the first electrode 300 and the second electrode 411, and a storage state is discriminated according to the magnitude of the current. The silver particles 103, which capture electric charges, are covered with the silver oxide 104 that serves as a barrier against the passage of electric charges, and therefore, the memory function body 113 can stably retain electric charges at the normal temperature.Type: GrantFiled: March 11, 2004Date of Patent: April 18, 2006Assignee: Sharp Kabushiki KaishaInventors: Nobutoshi Arai, Hiroshi Iwata, Seizo Kakimoto
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Patent number: 6969893Abstract: There is provided a semiconductor device of low power consumption and high reliability having DTMOS' and substrate-bias variable transistors, and portable electronic equipment using the semiconductor device. On a semiconductor substrate (11), trilayer well regions (12, 14, 16; 13, 15, 16) are formed, and DTMOS' (29, 30) and substrate-bias variable transistors (27, 28) are provided in the shallow well regions (16, 17). Large-width device isolation regions (181, 182, 183) are provided at boundaries forming PNP, NPN or NPNP structures, where a small-width device isolation region (18) is provided on condition that well regions on both sides are of an identical conductive type. Thus, a plurality of well regions of individual conductive types where substrate-bias variable transistors (27, 28) of individual conductive types are provided can be made electrically independent of one another, allowing the power consumption to be reduced. Besides, the latch-up phenomenon can be suppressed.Type: GrantFiled: November 13, 2001Date of Patent: November 29, 2005Assignee: Sharp Kabushiki KaishaInventors: Akihide Shibata, Hiroshi Iwata, Seizo Kakimoto
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Patent number: 6876055Abstract: A semiconductor device having a two-layer well structure and a small margin required at the boundary of a well region and comprising a substrate-bias variable transistor and a DTMOS. Field effect transistors (223) are formed on a P-type shallow well region (212). The depth of a shallow device isolation region (214) on the P-type shallow well region (212) is less than the depth of the junction between an N-type deep well region (227) and the P-type shallow well region (212). Therefore the field effect transistors (223) share the P-type shallow well region (212). The P-type shallow well regions (212) independently of each other are easily formed since they are isolated from each other by a deep device isolation region (226) and the N-type deep well region (227).Type: GrantFiled: October 19, 2001Date of Patent: April 5, 2005Assignee: Sharp Kabushiki KaishaInventors: Hiroshi Iwata, Akihide Shibata, Seizo Kakimoto
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Publication number: 20040262650Abstract: A semiconductor device 1910 comprises a semiconductor substrate 100 including an isolation region 101 and an active region 102, a gate electrode 104 provided on the active region 102 via a gate insulating film 103, part of a side of the gate electrode 104 being covered with a gate electrode side wall insulating film 105, and a source region 106 and a drain region 106 provided on opposite sides of the gate electrode 104 via the gate electrode side wall insulating film 105. At least one of the source region 106 and the drain region 106 has a second surface for contacting a contact conductor. The second surface is tilted with respect to a first surface A-A′. An angle between the second surface and a surface of the isolation region is 80 degrees or less.Type: ApplicationFiled: July 27, 2004Publication date: December 30, 2004Applicant: Sharp Kabushiki KaishaInventors: Hiroshi Iwata, Akihide Shibata, Seizo Kakimoto, Kouichiro Adachi, Masayuki Nakano
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Patent number: 6825528Abstract: A semiconductor device 1910 comprises a semiconductor substrate 100 including an isolation region 101 and an active region 102, a gate electrode 104 provided on the active region 102 via a gate insulating film 103, part of a side of the gate electrode 104 being covered with a gate electrode side wall insulating film 105, and a source region 106 and a drain region 106 provided on opposite sides of the gate electrode 104 via the gate electrode side wall insulating film 105. At least one of the source region 106 and the drain region 106 has a second surface for contacting a contact conductor. The second surface is tilted with respect to a first surface A-A′. An angle between the second surface and a surface of the isolation region is 80 degrees or less.Type: GrantFiled: August 12, 2002Date of Patent: November 30, 2004Assignee: Sharp Kabushiki KaishaInventors: Hiroshi Iwata, Akihide Shibata, Seizo Kakimoto, Kouichiro Adachi, Masayuki Nakano
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Publication number: 20040207011Abstract: A gate electrode sidewall conductive film 120 is formed via a gate electrode sidewall insulation film 119 on a sidewall of a gate electrode 118. By properly removing this gate electrode sidewall conductive film 120 by anisotropic etching that has selectivity to the gate electrode sidewall insulation film 119, isolation between a source region and a drain region and formation of local interconnections by the gate electrode sidewall conductive film 120 are concurrently achieved. Further, the gate electrode 118 is also properly removed by etching that has selectivity to the gate electrode sidewall insulation film 119, and therefore, the gate electrode interconnection is concurrently formed. Through the above process, there can be provided an SRAM device, which is allowed to have high integration by shrinking the memory cell area with simplified interconnections.Type: ApplicationFiled: April 29, 2004Publication date: October 21, 2004Inventors: Hiroshi Iwata, Akihide Shibata, Kotaro Kataoka, Seizo Kakimoto
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Publication number: 20040183647Abstract: A memory function body 113, which includes a plurality of silver particles 103 covered with silver oxide 104, is interposed between a first electrode 300 and a second electrode 411. A magnitude of a current through the memory function body 113 changes on applying a prescribed voltage between the first electrode 300 and the second electrode 411, and a storage state is discriminated according to the magnitude of the current. The silver particles 103, which capture electric charges, are covered with the silver oxide 104 that serves as a barrier against the passage of electric charges, and therefore, the memory function body 113 can stably retain electric charges at the normal temperature.Type: ApplicationFiled: March 11, 2004Publication date: September 23, 2004Inventors: Nobutoshi Arai, Hiroshi Iwata, Seizo Kakimoto
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Publication number: 20040180491Abstract: A memory function body has a medium interposed between a first conductor (e.g., a conductive substrate) and a second conductor (e.g., an electrode) and consisting of a first material (e.g., silicon oxide or silicon nitride). The medium contains particles. Each particle is covered with a second material (e.g., silver oxide) and formed of a third material (e.g., silver). The second material functions as a barrier against passage of electric charges, and the third material has a function of retaining electric charges. The third material is introduced into the medium by, for example, a negative ion implantation method.Type: ApplicationFiled: March 11, 2004Publication date: September 16, 2004Inventors: Nobutoshi Arai, Hiroshi Iwata, Seizo Kakimoto
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Patent number: 6787410Abstract: A semiconductor device with dynamic threshold transistors includes a complex element isolation region composed of a shallow element isolation region made of shallow trench isolation and deep element isolation regions provided on both sides of the shallow element isolation region. Since the shallow element isolation region is made of the shallow trench isolation, Bird's beak in the shallow element isolation region is small. This prevents off leakage failure due to stress caused by the bird's beak. The deep element isolation region has an approximately constant width which allows the complex element isolation region to be wide.Type: GrantFiled: December 19, 2002Date of Patent: September 7, 2004Assignee: Sharp Kabushiki KaishaInventors: Hiroshi Iwata, Akihide Shibata, Seizo Kakimoto