Abstract: A lateral double-diffused metal oxide semiconductor component and a manufacturing method therefor. The lateral double-diffused metal oxide semiconductor component comprises: a semiconductor substrate, the semiconductor substrate being provided thereon with a drift area; the drift area being provided therein with a trap area and a drain area, the trap area being provided therein with an active area and a channel; the drift area being provided therein with a deep trench isolation structure arranged between the trap area and the drain area, and the deep trench isolation structure being provided at the bottom thereof with alternately arranged first p-type injection areas and first n-type injection areas.

Abstract: A signal generation method and an electronic device pertain to the field of communications technologies, and include normalizing an I path of four-level signals and a Q path of four-level signals to obtain a normalized I path of four-level signals and a normalized Q path of four-level signals, mapping the normalized I path of four-level signals and the normalized Q path of four-level signals based on a normalization coefficient to obtain two paths of six-level signals, and driving a dual-drive Mach-Zehnder modulator (DDMZM) based on the six-level signals.

Abstract: This application discloses a flexible Ethernet group establishment method and a device. The method includes: determining that there are at least M physical layer PHY links; receiving at least M delay test requests sent by a near-end device; determining, by the far-end device, at least M receiving time points at which the at least M delay test requests are received; and determining M PHY links used to establish a flexible Ethernet group, from the at least M PHY links based on the at least M receiving time points, where a delay difference between any two of the M PHY links satisfies a preset delay condition. According to the method in this application, the delay difference between the any two PHY links is accurately determined based on time points at which delay test requests are received over any two PHY links.

Abstract: The invention discloses a preparation method of a polyimide film having a low dielectric constant and high fracture toughness; in the method an aromatic diamine solution is firstly prepared, and then a poly(5-norbornene-2,3-dicarboxylic anhydride-alt-maleimide isobutyl polyhedral oligomeric silsesquioxane) and aromatic dianhydride are ground, uniformly mixed, added to the aromatic diamine solution, and stirred to obtain a poly(5-norbornene-2,3-dicarboxylic anhydride-alt-maleimide isobutyl polyhedral oligomeric silsesquioxane)/polyamic acid solution; the solution is uniformly applied on a clean glass sheet, then placed in a vacuum drying oven, cooled to room temperature, and then a film is peeled off in water by ultrasonic and dried under vacuum to obtain the desired product. The dielectric constant of the film obtained by the invention is reduced to 2.

Abstract: A device integrated with a junction field-effect transistor, the device is divided into a JFET region and a power device area, and the device includes: a drain (201) having a first conduction type; and a first conduction type region (214) disposed on a front face of the drain; the JFET region further includes: a JFET source (208) having a first conduction type; a first well (202) having a second conduction type; a metal electrode (212) formed on the JFET source (208), which is in contact with the JFET source (208); a JFET metal gate (213) disposed on the first well (202) at both sides of the JFET source (208); and a first clamping region (210) located below the JFET metal gate (213) and within the first well (202).

Abstract: A device integrated with JFET, the device is divided into a JFET region and a power device region, and the device includes: a drain (201) with a first conduction type; and a first conduction type region disposed on a front surface of the drain (201); the JFET region includes: a first well (205) with a second conduction type and formed in the first conduction type region; a second well (207) with a second conduction type and formed in the first conduction type region; a JFET source (212) with the first conduction type; a metal electrode formed on the JFET source (212), which is in contact with the JFET source (212); and a second conduction type buried layer (203) formed under the JFET source (212) and the second well (207).

Abstract: A computer implemented method at an energy management system (EMS) controller apparatus for automatic generation of a SCADA (supervisory control and data acquisition) slave interface for an energy management system (EMS), includes storing a SCADA configuration file mapping SCADA data points to EMS data objects; providing the EMS data objects coded in statically typed programming language; providing site configuration information of the energy management system (EMS); scanning, by an object access framework (OAF), EMS data objects with EMS annotations and combining them with the site configuration information to generate an object binding repository (OBR); and compiling the SCADA configuration file to combine the SCADA data points mapping with the object binding repository to generate SCADA bindings information as part of the SCADA slave interface for the energy management system (EMS).

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming, on a substrate, an alternating dielectric stack including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating dielectric stack through the slit to form a plurality of horizontal trenches; forming a gate structure in each of the plurality of horizontal trenches; forming a spacer layer on sidewalls of the slit to cover the gate structures, wherein the spacer layer has a laminated structure; and forming a conductive wall in the slit, wherein the conductive wall is insulated from the gate structures by the spacer layer.

Abstract: A device integrated with a depletion-mode junction field-effect transistor and a method for manufacturing the device. The device includes: a well region, which is of a second conduction type and formed within a first conduction region (214); a JFET source (210), which is of a first conduction type and formed within the well region; a metal electrode (212) of the JFET sources formed on the JFET sources (210), which is in contact with the JFET sources (210); a lateral channel region (208), which is of the first conduction type and formed between two adjacent JFET sources (210), while two ends thereof are in contact with the two adjacent JFET sources (210); and a JFET metal gate (213) formed on the well region.

Abstract: The present invention discloses a leveling device for adjusting an installation gap between a first component and a second component. The first component and the second component respectively have a cooperative installation surface, the cooperative installation surface of the first component is provided with at least one leveling device; the leveling device comprises a driving device installed in the cooperative installation surface of the first component and an adjustment head rotatably connected to the driving device, the adjustment head moves upwardly or retracts downwardly relative to the cooperative installation surface of the first component; the driving device drives the adjustment head to protrude outside an installation position thereof and abut with the second component located on an opposite side of the installation position of the adjustment head to adjust the gap between the first and second component. The present invention relates to an easy-to-level display screen using the leveling device.

Abstract: A method for manufacturing a semiconductor device and an integrated semiconductor device, said method comprising: providing an epitaxial layer having a first region and a second region, forming, in the first region, at least two second doping-type deep wells, and forming, in the second region, at least two second doping-type deep wells; forming a first dielectric island between the second doping-type deep wells and forming a second dielectric island on the second doping-type deep wells; forming a first doping-type trench on two sides of the first dielectric island in the first region; forming a gate structure on the first dielectric island; and forming a separated first doping-type source region by using the second dielectric island as a mask, the first doping-type trench extending, in the first region, transversally to the first doping-type source region.

Abstract: A method and an apparatus for reducing noise of a switched reluctance motor, includes: supplying a PWM signal as a driving signal to a driving circuit of a switched reluctance motor; and varying a carrier frequency of the PWM signal as an operation period of the switched reluctance motor varies; if the switched reluctance motor changes phase, determining that the operation period of the switched reluctance motor varies.

Abstract: A semiconductor device includes a substrate (110); a buried layer (120) formed on the substrate (110), a diffusion layer (130) formed on the buried layer (120), wherein the diffusion layer (130) includes a first diffusion region (132) and a second diffusion region (134), and an impurity type of the second diffusion region (134) is opposite to an impurity type of the first diffusion region (132); the diffusion layer (134) further comprises a plurality of third diffusion regions (136) formed in the second diffusion region, wherein an impurity type of the third diffusion region (136) is opposite to the impurity type of the second diffusion region (134); and a gate (144) formed on the diffusion layer (130).

Abstract: A manufacturing method for a semiconductor device, and an integrated semiconductor device. The manufacturing method comprises: on a semiconductor substrate, forming an epitaxial layer having a first region, a second region, and a third region; forming at least one groove in the third region, forming at least two second doping deep traps in the first region, and forming at least two second doping deep traps in the second region; forming a first dielectric island between the second doping deep traps and forming a second dielectric island on the second doping deep traps; forming a first doping groove at both sides of the first dielectric island in the first region; forming a gate structure on the first dielectric island; forming an isolated first doping source region using the second dielectric island as a mask.

Abstract: The present application provides an integrated semiconductor device and an electronic apparatus, comprising a semiconductor substrate and a first doped epitaxial layer having a first region, a second region, and a third region; a partition structure is arranged in the third region; the first region is formed having at least two second doped deep wells, and the second region is formed having at least two second doped deep wells; a dielectric island partially covers a region between two adjacent doped deep wells in the first region and second region; a gate structure covers the dielectric island; a first doped source region is located on the two sides of the gate structure, and a first doped source region located in the same second doped deep well is separated; a first doped trench is located on the two sides of the dielectric island in the first region, and extends laterally to the first doped source region.

Abstract: The present invention discloses a guiding device and a self-unloading anti-separation display device for guiding a first component to move on a second component, wherein the first component and the second component respectively have a cooperative installation surface, and at least one of the cooperative installation surface of the first component and the cooperative installation surface of the second component is provided with at least one unloading device; the unloading device has a driving device and a pushing mechanism protruding towards the second component, and the pushing mechanism is butted with the second component to apply a counter force to the first component; the cooperative installation surface of the first component is provided with at least one guidepost; at least one guide hole is arranged at a position of the cooperative installation surface of the second component corresponding to the guidepost; the guidepost is inserted into the guide hole.

Abstract: An integrated circuit chip and a manufacturing method therefor, and a gate drive circuit, the integrated circuit chip comprising: a semiconductor substrate (103), a high voltage island (101a) being formed in the semiconductor substrate (103); a high voltage junction terminal (102a), the high voltage junction terminal (102a) surrounding the high voltage island (101a), a depletion type MOS device (N1) being formed on the high voltage junction terminal (102a), a gate electrode and a drain electrode of the depletion type MOS device (N1) being short connected, and a source electrode of the depletion type MOS device (N1) being connected to a high side power supply end (VB) of the integrated circuit chip; and a bipolar transistor (Q1), a collector electrode of the bipolar transistor (Q1) being short connected to the substrate and being connected to a low side power supply end (VCC) of the integrated circuit chip, an emitter of the bipolar transistor (Q1) being connected to a gate electrode of the depletion type MOS

Abstract: In one embodiment, a technique is provided for automating handover information from project (construction & design) to operation/maintenance. A schema-less repository is defined for holding handover asset objects and governing transformation automation. An information stitching method is defined for multiple-sourced project data integration and incorporating owners' requirement into the repository. A 2-step script-based transformation process is provided to encapsulate information modeling knowledge from a transformation definition.

Abstract: This disclosure provides a signal generation method and an electronic device, and pertains to the field of communications technologies. A mapping process is increased in this disclosure, to convert a four-level signal into a six-level signal, so that a dual-drive Mach-Zehnder modulator DDMZM is driven based on the six-level signal, thereby reducing a signal-to-noise ratio requirement of an input signal, improving a noise resistance capability of a transmit end, reducing impact from crosstalk between signals, and reducing a requirement standard on components such as a DAC and a driver. In addition, in embodiments of this disclosure, an amplitude requirement of a drive signal is greatly reduced, so that the amplitude requirement of the drive signal is reduced, and a power consumption requirement is further reduced, thereby reducing working pressure of the DDMZM, and improving overall system performance.

Abstract: The present invention discloses an unloading device and a self-unloading display device having a first component or a second component cooperatively installed, the first and the second component respectively have a cooperative installation surface, the cooperative installation surface of the first component is provided with at least one unloading device; the unloading device comprises a driving device and a pushing mechanism; the pushing mechanism is connected to a driving device in a transmission way, the pushing mechanism has at least a set of telescopic dowel bars, an end part of the dowel bar is an inclined surface, a small end formed by the inclined surface is arranged close to the cooperative installation surface of the first component; the driving device drives the dowel bar to move along the cooperative installation surface of the first component, the inclined surface of the dowel bar abuts with and moves along the second component.