Patents by Inventor Senaka Krishna Kanakamedala

Senaka Krishna Kanakamedala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10950629
    Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips laterally spaced apart by line trenches, and an alternating two-dimensional array of memory stack assemblies and dielectric pillar structures located in the line trenches. Each of the line trenches is filled with a respective laterally alternating sequence of memory stack assemblies and dielectric pillar structures. Each memory stack assembly includes a vertical semiconductor channel and a pair of memory film. The vertical semiconductor channel includes a semiconductor channel layer having large grains, which can be provided by a selective semiconductor growth from seed semiconductor material layers, sacrificial semiconductor material layers, or a single crystalline semiconductor material in a semiconductor substrate underlying the alternating stacks.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: March 16, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Fei Zhou, Senaka Krishna Kanakamedala, Yao-Sheng Lee
  • Publication number: 20200279868
    Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips laterally spaced apart by line trenches, and an alternating two-dimensional array of memory stack assemblies and dielectric pillar structures located in the line trenches. Each of the line trenches is filled with a respective laterally alternating sequence of memory stack assemblies and dielectric pillar structures. Each memory stack assembly includes a vertical semiconductor channel and a pair of memory film. The vertical semiconductor channel includes a semiconductor channel layer having large grains, which can be provided by a selective semiconductor growth from seed semiconductor material layers, sacrificial semiconductor material layers, or a single crystalline semiconductor material in a semiconductor substrate underlying the alternating stacks.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Inventors: Raghuveer S. Makala, Fei Zhou, Senaka Krishna Kanakamedala, Yao-Sheng Lee
  • Patent number: 10700086
    Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips laterally spaced apart by line trenches, and an alternating two-dimensional array of memory stack assemblies and dielectric pillar structures located in the line trenches. Each of the line trenches is filled with a respective laterally alternating sequence of memory stack assemblies and dielectric pillar structures. Each memory stack assembly includes a vertical semiconductor channel and a pair of memory film. The vertical semiconductor channel includes a semiconductor channel layer having large grains, which can be provided by a selective semiconductor growth from seed semiconductor material layers, sacrificial semiconductor material layers, or a single crystalline semiconductor material in a semiconductor substrate underlying the alternating stacks.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 30, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Fei Zhou, Senaka Krishna Kanakamedala, Yao-Sheng Lee
  • Publication number: 20200105595
    Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory stack structures through the alternating stack, forming a first backside trench and a second backside trench through the alternating stack, forming backside recesses by removing the sacrificial material layers, depositing a backside blocking dielectric layer after formation of the backside recesses, forming a liner that a lesser lateral extent than a lateral distance between the first backside trench and the second backside trench; and selectively growing a metal from surfaces of the liners while either not growing or growing at a lower rate the metal from surfaces of the backside recesses that are not covered by the liners.
    Type: Application
    Filed: November 19, 2019
    Publication date: April 2, 2020
    Inventors: Rahul SHARANGPANI, Raghuveer S. MAKALA, Fei ZHOU, Adarsh RAJASHEKHAR, Senaka Krishna KANAKAMEDALA, Fumitaka AMANO, Genta MIZUNO
  • Patent number: 10529620
    Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory stack structures through the alternating stack, forming a first backside trench and a second backside trench through the alternating stack, forming backside recesses by removing the sacrificial material layers, depositing a backside blocking dielectric layer after formation of the backside recesses, forming a liner that a lesser lateral extent than a lateral distance between the first backside trench and the second backside trench; and selectively growing a metal from surfaces of the liners while either not growing or growing at a lower rate the metal from surfaces of the backside recesses that are not covered by the liners.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: January 7, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Fei Zhou, Adarsh Rajashekhar, Senaka Krishna Kanakamedala, Fumitaka Amano, Genta Mizuno
  • Publication number: 20200006376
    Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips laterally spaced apart by line trenches, and an alternating two-dimensional array of memory stack assemblies and dielectric pillar structures located in the line trenches. Each of the line trenches is filled with a respective laterally alternating sequence of memory stack assemblies and dielectric pillar structures. Each memory stack assembly includes a vertical semiconductor channel and a pair of memory film. The vertical semiconductor channel includes a semiconductor channel layer having large grains, which can be provided by a selective semiconductor growth from seed semiconductor material layers, sacrificial semiconductor material layers, or a single crystalline semiconductor material in a semiconductor substrate underlying the alternating stacks.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Raghuveer S. Makala, Fei Zhou, Senaka Krishna Kanakamedala, Yao-Sheng Lee
  • Patent number: 10461163
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: October 29, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Senaka Krishna Kanakamedala, Yoshihiro Kanno, Raghuveer S. Makala, Yanli Zhang, Jin Liu, Murshed Chowdhury, Yao-Sheng Lee
  • Patent number: 10453854
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: October 22, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yoshihiro Kanno, Senaka Krishna Kanakamedala, Raghuveer S. Makala, Yanli Zhang, Jin Liu, Murshed Chowdhury
  • Patent number: 10438964
    Abstract: A strap level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. An array of memory stack structures is formed through the alternating stack and the strap level sacrificial layer. Each memory film in the memory stack structures includes a metal oxide blocking dielectric. After formation of a source cavity by removal of the strap level sacrificial layer, an atomic layer etch process can be employed to remove portions of the metal oxide blocking dielectrics at the level of the source cavity. Outer sidewalls of semiconductor channels in the memory stack structures are exposed by additional etch processes, and a source strap layer is selectively deposited in the source cavity in contact with the semiconductor channel. If the spacer material layers are sacrificial material layers, all volumes of the sacrificial material layers can be replaced with the electrically conductive layers.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: October 8, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Senaka Krishna Kanakamedala, Yanli Zhang, Yao-Sheng Lee
  • Patent number: 10381364
    Abstract: A three-dimensional memory device can be formed by first forming an alternating stack of insulating layers and stack level spacer material layers over a substrate. The stack level spacer material layers can be formed as, or are subsequently replaced with, stack level electrically conductive layers. A bottommost insulating spacer layer is formed with recesses that form grooves that are laterally spaced apart. Drain select level electrically conductive layers are formed over protruding portions and within the grooves of the bottommost insulating spacer layer by anisotropic deposition and isotropic etch back of a conductive material. Additional insulating spacer layers may be formed by anisotropic deposition of an insulating material. Additional drain select level electrically conductive layers can be formed by anisotropic deposition and isotropic etch back of additional conductive material.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fei Zhou, Rahul Sharangpani, Yanli Zhang, Raghuveer S. Makala, Senaka Krishna Kanakamedala
  • Publication number: 20190148392
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.
    Type: Application
    Filed: November 15, 2017
    Publication date: May 16, 2019
    Inventors: Yoshihiro KANNO, Senaka Krishna KANAKAMEDALA, Raghuveer S. MAKALA, Yanli ZHANG, Jin LIU, Murshed CHOWDHURY
  • Publication number: 20190148506
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.
    Type: Application
    Filed: November 15, 2017
    Publication date: May 16, 2019
    Inventors: Senaka Krishna KANAKAMEDALA, Yoshihiro KANNO, Raghuveer S. MAKALA, Yanli ZHANG, Jin LIU, Murshed CHOWDHURY, Yao-Sheng LEE
  • Patent number: 10199434
    Abstract: A phase change memory device includes a vertical stack of multiple two-dimensional arrays of pillar structures. Each of the multiple two-dimensional arrays of pillar structures is located within a respective array level. Each two-dimensional array among the multiple two-dimensional arrays of pillar structures is contacted by a respective overlying one-dimensional array of conductive rails laterally extending along a first horizontal direction and a respective underlying one-dimensional array of conductive rails laterally extending along a second horizontal direction different from the first direction. Each pillar structure within the multiple two-dimensional arrays of pillar structures includes a phase change memory element and a selector element in a series connection with the phase change memory element. A first set of dielectric isolation structures having a first homogeneous composition vertically extends continuously through two vertically neighboring array levels.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: February 5, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yao-Sheng Lee, Senaka Krishna Kanakamedala, Raghuveer S. Makala
  • Publication number: 20180374866
    Abstract: A strap level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. An array of memory stack structures is formed through the alternating stack and the strap level sacrificial layer. Each memory film in the memory stack structures includes a metal oxide blocking dielectric. After formation of a source cavity by removal of the strap level sacrificial layer, an atomic layer etch process can be employed to remove portions of the metal oxide blocking dielectrics at the level of the source cavity. Outer sidewalls of semiconductor channels in the memory stack structures are exposed by additional etch processes, and a source strap layer is selectively deposited in the source cavity in contact with the semiconductor channel. If the spacer material layers are sacrificial material layers, all volumes of the sacrificial material layers can be replaced with the electrically conductive layers.
    Type: Application
    Filed: June 26, 2017
    Publication date: December 27, 2018
    Inventors: Raghuveer S. MAKALA, Senaka Krishna KANAKAMEDALA, Yanli ZHANG, Yao-Sheng LEE
  • Publication number: 20180366482
    Abstract: A three-dimensional memory device can be formed by first forming an alternating stack of insulating layers and stack level spacer material layers over a substrate. The stack level spacer material layers can be formed as, or are subsequently replaced with, stack level electrically conductive layers. A bottommost insulating spacer layer is formed with recesses that form grooves that are laterally spaced apart. Drain select level electrically conductive layers are formed over protruding portions and within the grooves of the bottommost insulating spacer layer by anisotropic deposition and isotropic etch back of a conductive material. Additional insulating spacer layers may be formed by anisotropic deposition of an insulating material. Additional drain select level electrically conductive layers can be formed by anisotropic deposition and isotropic etch back of additional conductive material.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 20, 2018
    Inventors: Fei Zhou, Rahul Sharangpani, Yanli Zhang, Raghuveer S. Makala, Senaka Krishna Kanakamedala
  • Patent number: 10128261
    Abstract: A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: November 13, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Rahul Sharangpani, Sateesh Koka, Genta Mizuno, Naoki Takeguchi, Senaka Krishna Kanakamedala, George Matamis, Yao-Sheng Lee, Johann Alsmeier
  • Publication number: 20180090373
    Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory stack structures through the alternating stack, forming a first backside trench and a second backside trench through the alternating stack, forming backside recesses by removing the sacrificial material layers, depositing a backside blocking dielectric layer after formation of the backside recesses, forming a liner that a lesser lateral extent than a lateral distance between the first backside trench and the second backside trench; and selectively growing a metal from surfaces of the liners while either not growing or growing at a lower rate the metal from surfaces of the backside recesses that are not covered by the liners.
    Type: Application
    Filed: December 4, 2017
    Publication date: March 29, 2018
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Fei Zhou, Adarsh Rajashekhar, Senaka Krishna Kanakamedala, Fumitaka Amano, Genta Mizuno
  • Publication number: 20170287925
    Abstract: A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.
    Type: Application
    Filed: February 4, 2015
    Publication date: October 5, 2017
    Inventors: Raghuveer S. MAKALA, Rahul SHARANGPANI, Sateesh KOKA, Genta MIZUNO, Naoki TAKEGUCHI, Senaka Krishna KANAKAMEDALA, George MATAMIS, Yao-Sheng LEE, Johann ALSMEIER
  • Patent number: 9691884
    Abstract: Methods of making a monolithic three dimensional NAND string that include forming a stack of alternating first material layers and second material layers over a substrate, where each of the second material layers includes a layer of a first silicon oxide material between two layers of a second silicon oxide material different from the first silicon oxide material, etching the stack to form a front side opening in the stack, forming a memory film over a sidewall of the front side opening, and forming a semiconductor channel in the front side opening such that at least a portion of the memory film is located between the semiconductor channel and the sidewall of the front side opening, where at least one of an air gap or a material which has a dielectric constant below 3.9 is formed between the respective two layers of second silicon oxide material.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: June 27, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Yanli Zhang, Rahul Sharangpani, Yao-Sheng Lee, Senaka Krishna Kanakamedala, George Matamis, Johann Alsmeier
  • Patent number: 9570460
    Abstract: A method of making a semiconductor device includes forming a stack of alternating layers of a first material and a second material over a substrate, etching the stack to form at least one opening in the stack such that a damaged region is located on a bottom surface of the at least one opening, forming a masking layer on a sidewall of the at least one opening while the bottom surface of the at least one opening is not covered by the masking layer, and further etching the bottom surface of the at least one opening remove the damaged region.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: February 14, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Senaka Krishna Kanakamedala, Yao-Sheng Lee, Raghuveer S. Makala, George Matamis