Patents by Inventor Senani Gunaratna
Senani Gunaratna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10630269Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.Type: GrantFiled: November 19, 2018Date of Patent: April 21, 2020Assignee: Lattice Semiconductor CorporationInventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
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Patent number: 10382021Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.Type: GrantFiled: July 24, 2017Date of Patent: August 13, 2019Assignee: Lattice Semiconductor CorporationInventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
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Publication number: 20190158073Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.Type: ApplicationFiled: November 19, 2018Publication date: May 23, 2019Inventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
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Patent number: 10141917Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.Type: GrantFiled: July 24, 2017Date of Patent: November 27, 2018Assignee: Lattice Semiconductor CorporationInventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
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Patent number: 10079054Abstract: Various techniques are provided to efficiently implement selective power gating of routing resource configuration memory bits for programmable logic devices (PLDs). In one example, a PLD includes a routing circuit configured to selectively route input nodes to an output node. The PLD further includes configuration memory cells configured to store configuration bit values to control the routing circuit. The PLD further includes a power circuit configured to power the configuration memory cells while storing the configuration bit values. The PLD further includes an enable bit memory cell configured to store an enable bit value to interrupt at least one connection of the power circuit to the configuration memory cells. The configuration memory cells are configured to provide, in response to an interruption of the connection, default configuration bit values to the routing circuit to prevent routing the input nodes to the output node. Additional systems and related methods are provided.Type: GrantFiled: June 5, 2017Date of Patent: September 18, 2018Assignee: Lattice Semiconductor CorporationInventors: Senani Gunaratna, Brad Sharpe-Geisler, Ting Yew, Ronald L. Cline
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Publication number: 20170324400Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.Type: ApplicationFiled: July 24, 2017Publication date: November 9, 2017Inventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
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Publication number: 20170324401Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.Type: ApplicationFiled: July 24, 2017Publication date: November 9, 2017Inventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
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Patent number: 9735761Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.Type: GrantFiled: January 30, 2015Date of Patent: August 15, 2017Assignee: LATTICE SEMICONDUCTOR CORPORATIONInventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
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Patent number: 9716491Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.Type: GrantFiled: January 30, 2015Date of Patent: July 25, 2017Assignee: Lattice Semiconductor CorporationInventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
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Patent number: 9543950Abstract: A programmable logic is provided that uses only NMOS pass transistors to pass a true output signal to an internal true node and to pass a complement output signal to an internal complement node. The internal true and complement nodes are cross-coupled through PMOS transistors so that the discharge of one of the internal true and complement nodes switches on a corresponding one of the cross-coupled PMOS transistors to charge a remaining one of the internal true and complement nodes.Type: GrantFiled: January 30, 2015Date of Patent: January 10, 2017Assignee: LATTICE SEMICONDUCTOR CORPORATIONInventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
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Patent number: 9252755Abstract: A control circuit is provided that enables a register to provide a synchronous initialization capability as well as an asynchronous capability despite the register having no asynchronous input.Type: GrantFiled: January 30, 2015Date of Patent: February 2, 2016Assignee: LATTICE SEMICONDUCTOR CORPORATIONInventors: Brad Sharpe-Geisler, Ting Yew, Senani Gunaratna
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Publication number: 20160028383Abstract: A control circuit is provided that enables a register to provide a synchronous initialization capability as well as an asynchronous capability despite the register having no asynchronous input.Type: ApplicationFiled: January 30, 2015Publication date: January 28, 2016Inventors: Brad Sharpe-Geisler, Ting Yew, Senani Gunaratna
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Publication number: 20160028400Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.Type: ApplicationFiled: January 30, 2015Publication date: January 28, 2016Inventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
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Publication number: 20160028401Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.Type: ApplicationFiled: January 30, 2015Publication date: January 28, 2016Inventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
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Publication number: 20160020767Abstract: A programmable logic is provided that uses only NMOS pass transistors to pass a true output signal to an internal true node and to pass a complement output signal to an internal complement node. The internal true and complement nodes are cross-coupled through PMOS transistors so that the discharge of one of the internal true and complement nodes switches on a corresponding one of the cross-coupled PMOS transistors to charge a remaining one of the internal true and complement nodes.Type: ApplicationFiled: January 30, 2015Publication date: January 21, 2016Inventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
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Patent number: 8487652Abstract: An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different interface I/O demands of various dedicated devices that may be embedded into the integrated circuit. In one embodiment, the interface circuit may be implemented using a plurality of mask programmable uni-directional interface buffer circuits. The direction of any desired number of the interface buffer circuits can be reversed based on the needs of a desired dedicated device by re-routing the conductors in the interface buffer circuits in a single metal layer of the integrated circuit. In another embodiment, the interface circuit may be implemented using a hardware configurable bi-directional interface buffer circuit.Type: GrantFiled: August 18, 2011Date of Patent: July 16, 2013Assignee: QuickLogic CorporationInventors: Ket-Chong Yap, Senani Gunaratna, Wilma Waiman Shiao
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Publication number: 20110298492Abstract: An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different interface I/O demands of various dedicated devices that may be embedded into the integrated circuit. In one embodiment, the interface circuit may be implemented using a plurality of mask programmable uni-directional interface buffer circuits. The direction of any desired number of the interface buffer circuits can be reversed based on the needs of a desired dedicated device by re-routing the conductors in the interface buffer circuits in a single metal layer of the integrated circuit. In another embodiment, the interface circuit may be implemented using a hardware configurable bi-directional interface buffer circuit.Type: ApplicationFiled: August 18, 2011Publication date: December 8, 2011Applicant: QuickLogic CorporationInventors: Ket-Chong Yap, Senani Gunaratna, Wilma Waiman Shiao
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Patent number: 8018248Abstract: An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different interface I/O demands of various dedicated devices that may be embedded into the integrated circuit. In one embodiment, the interface circuit may be implemented using a plurality of mask programmable uni-directional interface buffer circuits. The direction of any desired number of the interface buffer circuits can be reversed based on the needs of a desired dedicated device by re-routing the conductors in the interface buffer circuits in a single metal layer of the integrated circuit. In another embodiment, the interface circuit may be implemented using a hardware configurable bi-directional interface buffer circuit.Type: GrantFiled: September 21, 2006Date of Patent: September 13, 2011Assignee: QuickLogic CorporationInventors: Ket-Chong Yap, Senani Gunaratna, Wilma Waiman Shiao
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Publication number: 20110074464Abstract: Circuits and power up sequences to reduce power consumption in programmable logic devices is disclosed.Type: ApplicationFiled: September 25, 2009Publication date: March 31, 2011Inventors: Senani Gunaratna, Kevin Norman, Timothy Garverick, Raminda Udaya Madurawe
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Patent number: 7443222Abstract: An implementation of an apparatus and method to generate a dynamically controlled clock is provided. The resulting clock reduces otherwise produced narrow clock pulses and allows for control from two separate control signals. A first control signal indicates a low power mode, for example a chip-wide low power mode. A second control signal indicates a user-selected mode to shutdown a selected clock.Type: GrantFiled: May 24, 2007Date of Patent: October 28, 2008Assignee: QuickLogic CorporationInventors: Timothy Saxe, Senani Gunaratna, Stephen U. Yao