Abstract: An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor layer, a source electrode, a drain electrode, and a sidewall spacer. The first patterned oxide semiconductor layer is disposed on the substrate. The source electrode and the drain electrode are disposed on the first patterned oxide semiconductor layer. The sidewall spacer is disposed on a sidewall of the first patterned oxide semiconductor layer. The sidewall spacer may be used to improve the performance of blocking impurities from entering the first patterned oxide semiconductor layer via the sidewall, and the electrical performance and the reliability of the oxide semiconductor device may be enhanced accordingly.

Abstract: An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor layer, a source electrode, a drain electrode, and a sidewall spacer. The first patterned oxide semiconductor layer is disposed on the substrate. The source electrode and the drain electrode are disposed on the first patterned oxide semiconductor layer. The sidewall spacer is disposed on a sidewall of the first patterned oxide semiconductor layer. The sidewall spacer may be used to improve the performance of blocking impurities from entering the first patterned oxide semiconductor layer via the sidewall, and the electrical performance and the reliability of the oxide semiconductor device may be enhanced accordingly.

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.

Abstract: A method for forming a semiconductor structure. A dielectric layer including adjacent first and second dielectric regions is formed on a substrate. The dielectric layer includes a curable material. The first dielectric region is cured. A portion of the second dielectric region is etched to form an opening and leave a remaining portion of the second dielectric region. After the etching step, the remaining portion of the second dielectric region is cured.

Abstract: A method for forming a semiconductor structure. A dielectric layer including adjacent first and second dielectric regions is formed on a substrate. The dielectric layer includes a curable material. The first dielectric region is cured. A portion of the second dielectric region is etched to form an opening and leave a remaining portion of the second dielectric region. After the etching step, the remaining portion of the second dielectric region is cured.

Abstract: An image sensor includes a plurality of color filters and an anti-reflective layer. The color filters are located on a substrate. The anti-reflective layer is located between the substrate and the color filters, and parts of the anti-reflective layer corresponding to at least two of the color filters have different thicknesses. Moreover, an image sensing process including the following steps is also provided. An anti-reflective layer is formed on a substrate. A plurality of color filters is formed on the anti-reflective layer, wherein parts of the anti-reflective layer right below at least two of the color filters have different thicknesses.

Abstract: An image sensor includes a plurality of color filters and an anti-reflective layer. The color filters are located on a substrate. The anti-reflective layer is located between the substrate and the color filters, and parts of the anti-reflective layer corresponding to at least two of the color filters have different thicknesses. Moreover, an image sensing process including the following steps is also provided. An anti-reflective layer is formed on a substrate. A plurality of color filters is formed on the anti-reflective layer, wherein parts of the anti-reflective layer right below at least two of the color filters have different thicknesses.

Abstract: A method for forming a semiconductor structure and a method for patterning a dielectric layer are provided. The method comprises following steps. An upper cap layer is formed on and physically contacted with a dielectric layer. The dielectric layer has a dielectric thickness having a range of 1000 ?˜5000 ?. A patterned mask layer is formed on and physically contacted with the upper cap layer. A part of the upper cap layer is removed to form a patterned upper cap layer by using the patterned mask layer as an etching mask. A part of the dielectric layer is removed to form a dielectric opening in the dielectric layer by using the patterned upper cap layer as an etching mask.

Abstract: A method for forming a dual damascene opening includes the following steps. Firstly, a first hard mask layer with a trench pattern is formed over a material layer. Then, a dielectric layer is formed over the first hard mask layer and filled into an opening of the trench pattern. Then, a second hard mask layer with a via opening pattern is formed over the first hard mask layer and the dielectric layer. Then, a first etching process is performed, so that a via opening is at least formed in the dielectric layer. After the second hard mask layer is removed, a second etching process is performed. Consequently, a trench opening is formed in the material layer and the via opening is further extended into the material layer, wherein the via opening is located within the trench opening.

Abstract: A method for forming a dual damascene opening includes the following steps. Firstly, a first hard mask layer with a trench pattern is formed over a material layer. Then, a dielectric layer is formed over the first hard mask layer and filled into an opening of the trench pattern. Then, a second hard mask layer with a via opening pattern is formed over the first hard mask layer and the dielectric layer. Then, a first etching process is performed, so that a via opening is at least formed in the dielectric layer. After the second hard mask layer is removed, a second etching process is performed. Consequently, a trench opening is formed in the material layer and the via opening is further extended into the material layer, wherein the via opening is located within the trench opening.