Patents by Inventor Seok Chin PHANG

Seok Chin PHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11163238
    Abstract: A technique which determines an optimum die layout on a semiconductor wafer is disclosed. The technique determines the optimum die layout with a significantly reduced number of calculations compared to conventional brute force techniques. This enables the generation of the optimum die layout in a much shorter period of time, reducing design turn-around time. The optimum layout is used to process a wafer which produces the optimum number of dies.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: November 2, 2021
    Assignee: Systems On Silicon Manufacturing Co. Pte. Ltd.
    Inventors: Seng Jian Tee, Seok Chin Phang
  • Publication number: 20210103223
    Abstract: A technique which determines an optimum die layout on a semiconductor wafer is disclosed. The technique determines the optimum die layout with a significantly reduced number of calculations compared to conventional brute force techniques. This enables the generation of the optimum die layout in a much shorter period of time, reducing design turn-around time. The optimum layout is used to process a wafer which produces the optimum number of dies.
    Type: Application
    Filed: October 4, 2019
    Publication date: April 8, 2021
    Inventors: Seng Jian TEE, Seok Chin PHANG