Patents by Inventor Seok Goh

Seok Goh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9130011
    Abstract: An apparatus for mounting a semiconductor device includes a mounting component and a loading component. The mounting component is configured to mount the semiconductor device onto a circuit board. The loading component is disposed adjacent to the mounting component, and is configured to supply the semiconductor device and the circuit board to the mounting component.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: September 8, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taehyun Kim, Dongsoo Lee, Seok Goh, Kyoungbok Cho
  • Publication number: 20140015129
    Abstract: A stacked package and method of manufacture are provided. The stacked package may include a first semiconductor package, a second semiconductor package, plugs and spacers. The second semiconductor package may be stacked on the first semiconductor package. The plugs may electrically connect the first semiconductor to the second semiconductor package. The spacer may be interposed between the first semiconductor package and the second semiconductor package to form a gap between the first semiconductor package and the second semiconductor package, thereby preventing an electrical short between the plugs.
    Type: Application
    Filed: September 17, 2013
    Publication date: January 16, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Geun KIM, Dong-Chul HAN, Seok GOH, Jeong-Hoon KIM
  • Patent number: 8564317
    Abstract: A test socket is provided that includes a socket body to receive an object to be tested, a lid disposed on the socket body, one or more pushers coupled to a first surface of lid to apply force to a first surface of the object toward the socket body, and a temperature controlling member to provide a temperature to the object. A semiconductor package may be tested in a test apparatus that includes the test socket, the methods of testing including receiving a semiconductor package in a socket in a test chamber, applying a first temperature to the test chamber to test the semiconductor package at a first test temperature, and applying a second temperature to the semiconductor package to test the semiconductor package at a second test temperature by controlling the application of the second temperature with the socket.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: October 22, 2013
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Jong-Won Han, Seok Goh, Byoung-Jun Min, Jung-Hyeon Kim, Sang-Sik Lee, Bo-Woo Kim, Ho-Jeong Choi
  • Patent number: 8546938
    Abstract: A stacked package and method of manufacture are provided. The stacked package may include a first semiconductor package, a second semiconductor package, plugs and spacers. The second semiconductor package may be stacked on the first semiconductor package. The plugs may electrically connect the first semiconductor to the second semiconductor package. The spacer may be interposed between the first semiconductor package and the second semiconductor package to form a gap between the first semiconductor package and the second semiconductor package, thereby preventing an electrical short between the plugs.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: October 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Geun Kim, Dong-Chul Han, Seok Goh, Jeong-Hoon Kim
  • Publication number: 20130074447
    Abstract: Carrier tape winding units and apparatuses of packing semiconductor package are provided. An exemplary carrier tape winding unit may include a carrier tape adhesion member attaching a front end of a carrier tape before winding or a cut back end of the carrier tape after a completion of winding the carrier tape to a winding reel. The exemplary carrier tape winding unit may further include a reel replacement member that automatically replaces the winding reel with another one after the completion of winding the carrier tape to the winding reel on a rotation axis by movement of a rotation axis and an axis support member in a direction. This direction is perpendicular to a transfer direction of the carrier tape toward the winding reel.
    Type: Application
    Filed: July 11, 2012
    Publication date: March 28, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ki-hun Kim, Seok Goh, Byoungjun Min, Poom-Seong Park, Donghae Son
  • Publication number: 20120205795
    Abstract: A stacked package and method of manufacture are provided. The stacked package may include a first semiconductor package, a second semiconductor package, plugs and spacers. The second semiconductor package may be stacked on the first semiconductor package. The plugs may electrically connect the first semiconductor to the second semiconductor package. The spacer may be interposed between the first semiconductor package and the second semiconductor package to form a gap between the first semiconductor package and the second semiconductor package, thereby preventing an electrical short between the plugs.
    Type: Application
    Filed: December 6, 2011
    Publication date: August 16, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Geun KIM, Dong-Chul HAN, Seok GOH, Jeong-Hoon KIM
  • Publication number: 20110232082
    Abstract: An apparatus for mounting a semiconductor device includes a mounting component and a loading component. The mounting component is configured to mount the semiconductor device onto a circuit board. The loading component is disposed adjacent to the mounting component, and is configured to supply the semiconductor device and the circuit board to the mounting component.
    Type: Application
    Filed: March 25, 2011
    Publication date: September 29, 2011
    Inventors: TAEHYUN KIM, Dongsoo Lee, Seok Goh, Kyoungbok Cho
  • Publication number: 20110079361
    Abstract: An apparatus for semiconductor die bonding includes a first bonding head and a second bonding head configured to respectively pickup a first semiconductor chip and a second semiconductor chip located at a pickup point. The apparatus for semiconductor die bonding may also include a first transfer device configured to transfer the first bonding head from the pickup point to a bonding point located on a substrate along a transfer path. The first transfer device may further be configured to return to the pickup point along a first return path after the first semiconductor chip is bonded to the substrate. Also, the apparatus for semiconductor die bonding may include a second transfer device configured to transfer the second bonding head from the pickup point to the bonding point located on the substrate along the transfer path. The second transfer device may further be configured to return to the pickup point along a second return path after the second semiconductor chip is bonded to the substrate.
    Type: Application
    Filed: August 4, 2010
    Publication date: April 7, 2011
    Inventors: Byeong-kuk Park, Seok Goh, Kyoung-bok Cho, Dong-soo Lee, Jung-hwan Woo
  • Publication number: 20100164525
    Abstract: A test socket is provided that includes a socket body to receive an object to be tested, a lid disposed on the socket body, one or more pushers coupled to a first surface of lid to apply force to a first surface of the object toward the socket body, and a temperature controlling member to provide a temperature to the object. A semiconductor package may be tested in a test apparatus that includes the test socket, the methods of testing including receiving a semiconductor package in a socket in a test chamber, applying a first temperature to the test chamber to test the semiconductor package at a first test temperature, and applying a second temperature to the semiconductor package to test the semiconductor package at a second test temperature by controlling the application of the second temperature with the socket.
    Type: Application
    Filed: March 8, 2010
    Publication date: July 1, 2010
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Jongwong HAN, Sangsik Lee, Seok Goh, Byoungjun Min, Jongpil Park, Jaemuk Oh, JungHyeon Kim
  • Patent number: 7485955
    Abstract: A variety of non-rectangular IC chips having a stepped or modified periphery or edge profile including one or more recessed or indented peripheral regions are provided for incorporation in modified package configurations, single chip packages and multi-chip assemblies, both stacked and/or planar. In the planar configurations, the recessed regions may be utilized, in cooperation with another appropriately sized IC chip, to increase the packing density of the resulting device. Similarly, in the stacked configuration, the recessed regions may be utilized to provide access to bond pads of lower chips and thereby reduce the need for spacers or peripheral thinning techniques and thereby improve the strength of the resulting assembly and/or reduce the overall height of the stacked structure.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: February 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-Ku Kang, Seok Goh, Jin-Ho Kim, Tae-Gyeong Chung, Yong-Jae Lee
  • Publication number: 20050205975
    Abstract: A variety of non-rectangular IC chips having a stepped or modified periphery or edge profile including one or more recessed or indented peripheral regions are provided for incorporation in modified package configurations, single chip packages and multi-chip assemblies, both stacked and/or planar. In the planar configurations, the recessed regions may be utilized, in cooperation with another appropriately sized IC chip, to increase the packing density of the resulting device. Similarly, in the stacked configuration, the recessed regions may be utilized to provide access to bond pads of lower chips and thereby reduce the need for spacers or peripheral thinning techniques and thereby improve the strength of the resulting assembly and/or reduce the overall height of the stacked structure.
    Type: Application
    Filed: March 11, 2005
    Publication date: September 22, 2005
    Inventors: In-Ku Kang, Seok Goh, Jin-Ho Kim, Tae-Gyeong Chung, Yong-Jae Lee
  • Publication number: 20040185580
    Abstract: A method for dicing semiconductor wafers is provided in which data present on the primary surface of the semiconductor wafers is recognized and used to controlling the cutting operation. The combination of the controller and the cutting means allows for the cutting of complex and non-linear shapes and allows for the combination of more than one semiconductor chip edge profile on a semiconductor wafer. The cutting means is preferably a laser or other cutting device capable of cutting fine patterns without causing undue damage to the semiconductor wafer or the resulting semiconductor chips. The more complex profiles of the semiconductor chips that may be produced with this method may, in turn, be utilized to improve the density within semiconductor device packages and/or on mounting substrates such as a printed circuit boards. The present invention can, therefore, improve space utilization, reduce fabrication expenses, reduce processing time and simplify package manufacture.
    Type: Application
    Filed: March 22, 2004
    Publication date: September 23, 2004
    Inventor: Seok Goh
  • Patent number: 6698486
    Abstract: An apparatus for removing a wafer ring tape, on which defective chips remain, from a wafer ring after normal chips are detached from the wafer ring tape, is provided. The apparatus comprises a ring table for supporting a tape-adhered wafer ring in which the wafer ring tape is attached to the wafer ring; a detaching head positionable above the ring table and movable for detaching the wafer ring tape from the wafer ring; a blocking pin disposed under the ring table to support the wafer ring tape detached from the wafer ring; and a pair of compressing plates disposed under the ring table to compress the wafer ring tape supported by the blocking pin.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: March 2, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok Goh
  • Patent number: 6408507
    Abstract: Automated equipment mounts heat sinks on printed circuit boards. First heat sinks, semiconductor modules and second heat sinks are consecutively seated on a plurality of built-up pads as the built-up pads move from station to station around a built-up pad conveyer. Rivets are mounted in a first heat sink and inserted through holes in a semiconductor module and a second heat sink when seating the semiconductor module and the second heat sink. Working the rivets fixes the first heat sink, the semiconductor module and the second heat sink permanently, and thereby forms a semiconductor product. After that, a label is attached on the semiconductor product and the riveting quality and the labeling quality of the semiconductor product are inspected.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: June 25, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok Goh
  • Publication number: 20020070302
    Abstract: An apparatus for removing a wafer ring tape, on which defective chips remain, from a wafer ring after normal chips are detached from the wafer ring tape, is provided. The apparatus comprises a ring table for supporting a tape-adhered wafer ring in which the wafer ring tape is attached to the wafer ring; a detaching head positionable above the ring table and movable for detaching the wafer ring tape from the wafer ring; a blocking pin disposed under the ring table to support the wafer ring tape detached from the wafer ring; and a pair of compressing plates disposed under the ring table to compress the wafer ring tape supported by the blocking pin.
    Type: Application
    Filed: December 6, 2001
    Publication date: June 13, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Seok Goh
  • Patent number: 6343503
    Abstract: A module appearance inspection apparatus includes a warpage checking unit, a visual checking unit, a first module transfer unit for unloading the module from a module tray, a second module transfer unit for transferring the module within the apparatus, and a third module transfer unit for loading the module to a module tray. The apparatus can replace the first and third module transfer units with a single module transfer unit. In this case, the apparatus includes: a warpage checking unit; a visual checking unit; a supply unit in which module trays are stacked; a storage unit in which module trays also can be stacked; a tray transfer unit which moves a module tray from the supply unit to the storage unit; a first module transfer unit which unloads and loads the module from and to the module tray on the tray transfer unit; and a second module transfer unit which transfers the module from the warpage checking unit or the visual checking unit.
    Type: Grant
    Filed: December 6, 1999
    Date of Patent: February 5, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok Goh