Patents by Inventor Seok-Han Park

Seok-Han Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11031338
    Abstract: A semiconductor device includes a first interlayer insulating film on a substrate, a via which penetrates the first interlayer insulating film, a first etching stop film which extends along an upper surface of the first interlayer insulating film, a second interlayer insulating film on the first etching stop film, the second interlayer insulating film including a plurality of periodically arranged air gaps, a first wiring pattern in the second interlayer insulating film, the first wiring pattern penetrating the first etching stop film and is connected to the via, and a capping film which covers an upper surface of the second interlayer insulating film and an upper surface of the first wiring pattern, each of the plurality of air gaps in the second interlayer insulating film extending from the first etching stop film to the capping film.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Seok Han Park
  • Patent number: 11018020
    Abstract: A method of fabricating an integrated circuit device includes forming a mold layer on a main surface of a substrate. A first hole is formed in the mold layer having a first inner wall that has a first tilt angle. A first conductive pattern is formed in the first hole. A block copolymer layer is formed on the mold layer and the first conductive pattern. A self-assembly layer is formed having a first domain and a second domain by phase separation of the block copolymer layer. The first domain covers the first conductive pattern and the second domain covers the mold layer. A second hole is formed by removing the first domain, the second hole having a second inner wall that has a second tilt angle. A second conductive pattern is formed in the second hole.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: May 25, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Seok-han Park
  • Patent number: 10998324
    Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: May 4, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki Wook Jung, Dong Oh Kim, Seok Han Park, Chan Sic Yoon, Ki Seok Lee, Ho In Lee, Ju Yeon Jang, Je Min Park, Jin Woo Hong
  • Patent number: 10950510
    Abstract: A semiconductor device includes a base substrate, a protruding structure on the base substrate, a porous film on a side surface and an upper surface of the protruding structure, and an air gap between at least a part of the side surface of the protruding structure and the porous film.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: March 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok Han Park
  • Publication number: 20210074914
    Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction, a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, and a variable resistive material on the semiconductor layer, a vacancy concentration in the variable resistive material varies along its width to have a higher concentration closer to a center of the channel structure than to the semiconductor layer, and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.
    Type: Application
    Filed: October 3, 2019
    Publication date: March 11, 2021
    Inventors: Kyung Hwan LEE, Yong Seok KIM, Tae Hun KIM, Seok Han PARK, Satoru YAMADA, Jae Ho HONG
  • Patent number: 10937729
    Abstract: Described herein is an integrated circuit device comprising a conductive line structure including a bit line and an insulating capping pattern; and an insulating spacer covering a side wall of the conductive line structure, the insulating spacer including an inner spacer and a char spacer. To form the insulating spacer, a polymer brush pattern may be chemically bonded to the inner spacer to cover a side wall of the conductive line structure; a first insulating spacer film covering the inner spacer and the polymer brush pattern may be formed; and a char spacer may be formed from the polymer brush pattern by pyrolyzing the polymer brush pattern in the absence of oxygen.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: March 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-han Park
  • Patent number: 10916623
    Abstract: A semiconductor device including one or more switches on a substrate, a first electrode connected to the one or more switches and having a helical shape defining a spiral groove, a support in contact with the first electrode, the spiral groove extending between the support and a portion of the first electrode, a capacitor dielectric layer in contact with the first electrode, and a second electrode in contact with the capacitor dielectric layer.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: February 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Seok Han Park
  • Publication number: 20210036020
    Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.
    Type: Application
    Filed: July 29, 2020
    Publication date: February 4, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seok Han PARK, Yong Seok KIM, Hui-Jung KIM, Satoru YAMADA, Kyung Hwan LEE, Jae Ho HONG, Yoo Sang HWANG
  • Publication number: 20200295013
    Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.
    Type: Application
    Filed: June 2, 2020
    Publication date: September 17, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ki Wook Jung, Dong Oh Kim, Seok Han Park, Chan Sic Yoon, Ki Seok Lee, Ho In Lee, Ju Yeon Jang, Je Min Park, Jin Woo Hong
  • Patent number: 10727233
    Abstract: An integrated circuit device includes: a conductive line structure including a conductive line and an insulating capping pattern; and an insulating spacer including an inner spacer and a first insulating spacer, the inner spacer and the first insulating spacer on a sidewall of the conductive line structure. The first insulating spacer includes: a slit portion; a lower insulating portion spaced apart from the inner spacer such that a separation distance between a portion of the lower insulating portion and the inner spacer decreases with increasing vertical distance from the substrate; and an upper insulating portion contacting the inner spacer. A method of forming the insulating spacer includes: forming a polymer layer on the inner spacer; forming a first insulating spacer layer which contacts each of the inner spacer and the polymer layer; and forming a first insulating spacer by partially removing the first insulating spacer layer.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: July 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-han Park
  • Publication number: 20200212170
    Abstract: A semiconductor device including one or more switches on a substrate, a first electrode connected to the one or more switches and having a helical shape defining a spiral groove, a support in contact with the first electrode, the spiral groove extending between the support and a portion of the first electrode, a capacitor dielectric layer in contact with the first electrode, and a second electrode in contact with the capacitor dielectric layer.
    Type: Application
    Filed: May 15, 2019
    Publication date: July 2, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Seok Han PARK
  • Publication number: 20200203239
    Abstract: A semiconductor device includes a base substrate, a protruding structure on the base substrate, a porous film on a side surface and an upper surface of the protruding structure, and an air gap between at least a part of the side surface of the protruding structure and the porous film.
    Type: Application
    Filed: August 12, 2019
    Publication date: June 25, 2020
    Inventor: Seok Han PARK
  • Publication number: 20200203275
    Abstract: A semiconductor device includes a first interlayer insulating film on a substrate, a via which penetrates the first interlayer insulating film, a first etching stop film which extends along an upper surface of the first interlayer insulating film, a second interlayer insulating film on the first etching stop film, the second interlayer insulating film including a plurality of periodically arranged air gaps, a first wiring pattern in the second interlayer insulating film, the first wiring pattern penetrating the first etching stop film and is connected to the via, and a capping film which covers an upper surface of the second interlayer insulating film and an upper surface of the first wiring pattern, each of the plurality of air gaps in the second interlayer insulating film extending from the first etching stop film to the capping film.
    Type: Application
    Filed: August 1, 2019
    Publication date: June 25, 2020
    Inventor: Seok Han PARK
  • Patent number: 10679997
    Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: June 9, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki Wook Jung, Dong Oh Kim, Seok Han Park, Chan Sic Yoon, Ki Seok Lee, Ho In Lee, Ju Yeon Jang, Je Min Park, Jin Woo Hong
  • Publication number: 20200118920
    Abstract: Described herein is an integrated circuit device comprising a conductive line structure including a bit line and an insulating capping pattern; and an insulating spacer covering a side wall of the conductive line structure, the insulating spacer including an inner spacer and a char spacer. To form the insulating spacer, a polymer brush pattern may be chemically bonded to the inner spacer to cover a side wall of the conductive line structure; a first insulating spacer film covering the inner spacer and the polymer brush pattern may be formed; and a char spacer may be formed from the polymer brush pattern by pyrolyzing the polymer brush pattern in the absence of oxygen.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventor: Seok-han Park
  • Publication number: 20200105540
    Abstract: A method of fabricating an integrated circuit device includes forming a mold layer on a main surface of a substrate. A first hole is formed in the mold layer having a first inner wall that has a first tilt angle. A first conductive pattern is formed in the first hole. A block copolymer layer is formed on the mold layer and the first conductive pattern. A self-assembly layer is formed having a first domain and a second domain by phase separation of the block copolymer layer. The first domain covers the first conductive pattern and the second domain covers the mold layer. A second hole is formed by removing the first domain, the second hole having a second inner wall that has a second tilt angle. A second conductive pattern is formed in the second hole.
    Type: Application
    Filed: April 16, 2019
    Publication date: April 2, 2020
    Inventor: Seok-han Park
  • Patent number: 10573652
    Abstract: A semiconductor device includes a substrate having a trench, a bit line in the trench, a first spacer extending along the trench and at least a portion of a side surface of the bit line and in contact with the bit line, and a second spacer disposed within the trench on the first spacer. The bit line is narrower than the trench, and the first spacer includes silicon oxide. A method of forming a semiconductor device includes forming a trench in a substrate, forming a bit line within the first trench of width less than that of the first trench, and forming a first spacer that lines a portion of the trench and includes silicon oxide in contact with at least a portion of a side surface of the bit line, and forming a second spacer over the first spacer in the trench.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: February 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myeong-Dong Lee, Jun-Won Lee, Ki Seok Lee, Bong-Soo Kim, Seok Han Park, Sung Hee Han, Yoo Sang Hwang
  • Patent number: 10546810
    Abstract: Described herein is an integrated circuit device comprising a conductive line structure including a bit line and an insulating capping pattern; and an insulating spacer covering a side wall of the conductive line structure, the insulating spacer including an inner spacer and a char spacer. To form the insulating spacer, a polymer brush pattern may be chemically bonded to the inner spacer to cover a side wall of the conductive line structure; a first insulating spacer film covering the inner spacer and the polymer brush pattern may be formed; and a char spacer may be formed from the polymer brush pattern by pyrolyzing the polymer brush pattern in the absence of oxygen.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: January 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-han Park
  • Publication number: 20190252393
    Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.
    Type: Application
    Filed: April 23, 2019
    Publication date: August 15, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ki Wook JUNG, Dong Oh KIM, Seok Han PARK, Chan Sic YOON, Ki Seok LEE, Ho ln LEE, Ju Yeon JANG, Je Min PARK, Jin Woo HONG
  • Patent number: 10332894
    Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: June 25, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki Wook Jung, Dong Oh Kim, Seok Han Park, Chan Sic Yoon, Ki Seok Lee, Ho In Lee, Ju Yeon Jang, Je Min Park, Jin Woo Hong