Patents by Inventor Seok-Han Park
Seok-Han Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11963364Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.Type: GrantFiled: September 28, 2022Date of Patent: April 16, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Seok Han Park, Yong Seok Kim, Hui-Jung Kim, Satoru Yamada, Kyung Hwan Lee, Jae Ho Hong, Yoo Sang Hwang
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Publication number: 20240105963Abstract: A method for manufacturing a gas diffusion layer for a fuel cell wherein carbon nanotubes are impregnated into Korean paper, thereby enhancing electroconductivity, and a gas diffusion layer manufactured thereby. The method for manufacturing a gas diffusion layer for a fuel cell which is to manufacture a gas diffusion layer as a constituent member of a unit cell in a fuel cell, includes a support preparation step of preparing a support with Korean paper; a dispersion preparation step of dispersing a carbon substance in a solvent to form a dispersion, a coating step of coating the support with the dispersion, and a thermal treatment step of thermally treating the dispersion-coated support to fix the carbon substance to the support.Type: ApplicationFiled: March 6, 2023Publication date: March 28, 2024Inventors: Seung Tak Noh, Ji Han Lee, In Seok Lee, Jae Man Park, Won Jong Choi, Choong Hee Kim, Seong Hwang Kim, Jong Hoon Lee, Soo Jin Park, Seul Yi Lee
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Publication number: 20230371243Abstract: A semiconductor memory device includes a peripheral gate structure disposed on a substrate, a bit line disposed on the peripheral gate structure and extending in a first direction, a shielding structure disposed adjacent to the bit line on the peripheral gate structure and extending in the first direction, a first word line disposed on the bit line and the shielding structure and extending in a second direction, a second word line disposed on the bit line and the shielding structure, extending in the second direction, and spaced apart from the first word line in the first direction, first and second active patterns disposed on the bit line and disposed between the first and second word lines, and contact patterns connected to the first and second active patterns.Type: ApplicationFiled: January 26, 2023Publication date: November 16, 2023Inventors: Ki Seok LEE, Keun Nam KIM, Seok Han PARK
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Patent number: 11723290Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction, a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, and a variable resistive material on the semiconductor layer, a vacancy concentration in the variable resistive material varies along its width to have a higher concentration closer to a center of the channel structure than to the semiconductor layer, and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.Type: GrantFiled: October 29, 2021Date of Patent: August 8, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyung Hwan Lee, Yong Seok Kim, Tae Hun Kim, Seok Han Park, Satoru Yamada, Jae Ho Hong
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Publication number: 20230019055Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.Type: ApplicationFiled: September 28, 2022Publication date: January 19, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Seok Han PARK, Yong Seok KIM, Hui-Jung KIM, Satoru YAMADA, Kyung Hwan LEE, Jae Ho HONG, Yoo Sang HWANG
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Patent number: 11476194Abstract: A semiconductor device includes a first interlayer insulating film on a substrate, a via which penetrates the first interlayer insulating film, a first etching stop film which extends along an upper surface of the first interlayer insulating film, a second interlayer insulating film on the first etching stop film, the second interlayer insulating film including a plurality of periodically arranged air gaps, a first wiring pattern in the second interlayer insulating film, the first wiring pattern penetrating the first etching stop film and is connected to the via, and a capping film which covers an upper surface of the second interlayer insulating film and an upper surface of the first wiring pattern, each of the plurality of air gaps in the second interlayer insulating film extending from the first etching stop film to the capping film.Type: GrantFiled: May 11, 2021Date of Patent: October 18, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Seok Han Park
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Patent number: 11469252Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.Type: GrantFiled: July 29, 2020Date of Patent: October 11, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Seok Han Park, Yong Seok Kim, Hui-Jung Kim, Satoru Yamada, Kyung Hwan Lee, Jae Ho Hong, Yoo Sang Hwang
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Publication number: 20220052257Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction, a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, and a variable resistive material on the semiconductor layer, a vacancy concentration in the variable resistive material varies along its width to have a higher concentration closer to a center of the channel structure than to the semiconductor layer, and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.Type: ApplicationFiled: October 29, 2021Publication date: February 17, 2022Inventors: Kyung Hwan LEE, Yong Seok KIM, Tae Hun KIM, Seok Han PARK, Satoru YAMADA, Jae Ho HONG
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Patent number: 11165018Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction, a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, and a variable resistive material on the semiconductor layer, a vacancy concentration in the variable resistive material varies along its width to have a higher concentration closer to a center of the channel structure than to the semiconductor layer, and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.Type: GrantFiled: October 3, 2019Date of Patent: November 2, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyung Hwan Lee, Yong Seok Kim, Tae Hun Kim, Seok Han Park, Satoru Yamada, Jae Ho Hong
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Publication number: 20210265270Abstract: A semiconductor device includes a first interlayer insulating film on a substrate, a via which penetrates the first interlayer insulating film, a first etching stop film which extends along an upper surface of the first interlayer insulating film, a second interlayer insulating film on the first etching stop film, the second interlayer insulating film including a plurality of periodically arranged air gaps, a first wiring pattern in the second interlayer insulating film, the first wiring pattern penetrating the first etching stop film and is connected to the via, and a capping film which covers an upper surface of the second interlayer insulating film and an upper surface of the first wiring pattern, each of the plurality of air gaps in the second interlayer insulating film extending from the first etching stop film to the capping film.Type: ApplicationFiled: May 11, 2021Publication date: August 26, 2021Inventor: Seok Han PARK
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Publication number: 20210246044Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.Type: ApplicationFiled: April 13, 2021Publication date: August 12, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Ki Wook JUNG, Dong Oh KIM, Seok Han PARK, Chan Sic YOON, Ki Seok LEE, Ho In LEE, Ju Yeon JANG, Je Min PARK, Jin Woo HONG
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Patent number: 11031338Abstract: A semiconductor device includes a first interlayer insulating film on a substrate, a via which penetrates the first interlayer insulating film, a first etching stop film which extends along an upper surface of the first interlayer insulating film, a second interlayer insulating film on the first etching stop film, the second interlayer insulating film including a plurality of periodically arranged air gaps, a first wiring pattern in the second interlayer insulating film, the first wiring pattern penetrating the first etching stop film and is connected to the via, and a capping film which covers an upper surface of the second interlayer insulating film and an upper surface of the first wiring pattern, each of the plurality of air gaps in the second interlayer insulating film extending from the first etching stop film to the capping film.Type: GrantFiled: August 1, 2019Date of Patent: June 8, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Seok Han Park
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Patent number: 11018020Abstract: A method of fabricating an integrated circuit device includes forming a mold layer on a main surface of a substrate. A first hole is formed in the mold layer having a first inner wall that has a first tilt angle. A first conductive pattern is formed in the first hole. A block copolymer layer is formed on the mold layer and the first conductive pattern. A self-assembly layer is formed having a first domain and a second domain by phase separation of the block copolymer layer. The first domain covers the first conductive pattern and the second domain covers the mold layer. A second hole is formed by removing the first domain, the second hole having a second inner wall that has a second tilt angle. A second conductive pattern is formed in the second hole.Type: GrantFiled: April 16, 2019Date of Patent: May 25, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Seok-han Park
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Patent number: 10998324Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.Type: GrantFiled: June 2, 2020Date of Patent: May 4, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Ki Wook Jung, Dong Oh Kim, Seok Han Park, Chan Sic Yoon, Ki Seok Lee, Ho In Lee, Ju Yeon Jang, Je Min Park, Jin Woo Hong
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Patent number: 10950510Abstract: A semiconductor device includes a base substrate, a protruding structure on the base substrate, a porous film on a side surface and an upper surface of the protruding structure, and an air gap between at least a part of the side surface of the protruding structure and the porous film.Type: GrantFiled: August 12, 2019Date of Patent: March 16, 2021Assignee: Samsung Electronics Co., Ltd.Inventor: Seok Han Park
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Publication number: 20210074914Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction, a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, and a variable resistive material on the semiconductor layer, a vacancy concentration in the variable resistive material varies along its width to have a higher concentration closer to a center of the channel structure than to the semiconductor layer, and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.Type: ApplicationFiled: October 3, 2019Publication date: March 11, 2021Inventors: Kyung Hwan LEE, Yong Seok KIM, Tae Hun KIM, Seok Han PARK, Satoru YAMADA, Jae Ho HONG
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Patent number: 10937729Abstract: Described herein is an integrated circuit device comprising a conductive line structure including a bit line and an insulating capping pattern; and an insulating spacer covering a side wall of the conductive line structure, the insulating spacer including an inner spacer and a char spacer. To form the insulating spacer, a polymer brush pattern may be chemically bonded to the inner spacer to cover a side wall of the conductive line structure; a first insulating spacer film covering the inner spacer and the polymer brush pattern may be formed; and a char spacer may be formed from the polymer brush pattern by pyrolyzing the polymer brush pattern in the absence of oxygen.Type: GrantFiled: December 16, 2019Date of Patent: March 2, 2021Assignee: Samsung Electronics Co., Ltd.Inventor: Seok-han Park
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Patent number: 10916623Abstract: A semiconductor device including one or more switches on a substrate, a first electrode connected to the one or more switches and having a helical shape defining a spiral groove, a support in contact with the first electrode, the spiral groove extending between the support and a portion of the first electrode, a capacitor dielectric layer in contact with the first electrode, and a second electrode in contact with the capacitor dielectric layer.Type: GrantFiled: May 15, 2019Date of Patent: February 9, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Seok Han Park
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Publication number: 20210036020Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.Type: ApplicationFiled: July 29, 2020Publication date: February 4, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Seok Han PARK, Yong Seok KIM, Hui-Jung KIM, Satoru YAMADA, Kyung Hwan LEE, Jae Ho HONG, Yoo Sang HWANG
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Publication number: 20200295013Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.Type: ApplicationFiled: June 2, 2020Publication date: September 17, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Ki Wook Jung, Dong Oh Kim, Seok Han Park, Chan Sic Yoon, Ki Seok Lee, Ho In Lee, Ju Yeon Jang, Je Min Park, Jin Woo Hong