Patents by Inventor Seok Ho Shin

Seok Ho Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11930526
    Abstract: Disclosed are methods and apparatuses for transmitting data using a random access procedure in a communication system. An operation method of a terminal in a communication system includes transmitting a first MsgA including an RA preamble #i and a payload to a base station; receiving, from the base station, a MsgB including information indicating that an RA preamble #k is reserved; and transmitting a second MsgA including the RA preamble #k and data to the base station in a preamble reservation period associated with the RA preamble #k.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: March 12, 2024
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Ok Sun Park, Seok Ki Kim, Gi Yoon Park, Eun Jeong Shin, Jae Sheung Shin, Jin Ho Choi
  • Patent number: 11177264
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including a plurality of active regions that extend longitudinally in a direction and an isolation region that electrically isolates the plurality of active regions from each other. The semiconductor device includes a gate trench that extends across the plurality of active regions and the isolation region. The semiconductor device includes a gate structure that extends in the gate trench. The semiconductor device includes a gate dielectric layer that is between the gate trench and the gate structure, in each of the plurality of active regions. The gate structure has a first width in the direction in each of the plurality of active regions and has a second width in the direction in the isolation region that is different from the first width.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: November 16, 2021
    Inventors: Jae-hyeon Jeon, Se-keun Park, Dong-sik Park, Seok-ho Shin
  • Patent number: 10854562
    Abstract: A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a plurality of connection structures provided in a lower insulating layer of the edge region and arranged at first intervals in a first direction, an upper insulating layer covering the connection structures, and a plurality of redistribution pads disposed on the upper insulating layer and connected to the connection structures, respectively. Each of the redistribution pads includes a pad portion provided on the chip region. The pad portions of the redistribution pads are spaced apart from the connection structures by a first distance in a second direction intersecting the first direction when viewed in a plan view.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: December 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Ho Shin, Bonhwi Gu, Hyekyeong Kweon, Sungjin Kim, Joodong Kim, Jaepil Lee, Dongwon Lim
  • Publication number: 20200266162
    Abstract: A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a plurality of connection structures provided in a lower insulating layer of the edge region and arranged at first intervals in a first direction, an upper insulating layer covering the connection structures, and a plurality of redistribution pads disposed on the upper insulating layer and connected to the connection structures, respectively. Each of the redistribution pads includes a pad portion provided on the chip region. The pad portions of the redistribution pads are spaced apart from the connection structures by a first distance in a second direction intersecting the first direction when viewed in a plan view.
    Type: Application
    Filed: May 6, 2020
    Publication date: August 20, 2020
    Inventors: SEOK-HO SHIN, BONHWI GU, HYEKYEONG KWEON, SUNGJIN KIM, JOODONG KIM, JAEPIL LEE, DONGWON LIM
  • Patent number: 10679957
    Abstract: A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a plurality of connection structures provided in a lower insulating layer of the edge region and arranged at first intervals in a first direction, an upper insulating layer covering the connection structures, and a plurality of redistribution pads disposed on the upper insulating layer and connected to the connection structures, respectively. Each of the redistribution pads includes a pad portion provided on the chip region. The pad portions of the redistribution pads are spaced apart from the connection structures by a first distance in a second direction intersecting the first direction when viewed in a plan view.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: June 9, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Ho Shin, Bonhwi Gu, Hyekyeong Kweon, Sungjin Kim, Joodong Kim, Jaepil Lee, Dongwon Lim
  • Publication number: 20200168611
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including a plurality of active regions that extend longitudinally in a direction and an isolation region that electrically isolates the plurality of active regions from each other. The semiconductor device includes a gate trench that extends across the plurality of active regions and the isolation region. The semiconductor device includes a gate structure that extends in the gate trench. The semiconductor device includes a gate dielectric layer that is between the gate trench and the gate structure, in each of the plurality of active regions. The gate structure has a first width in the direction in each of the plurality of active regions and has a second width in the direction in the isolation region that is different from the first width.
    Type: Application
    Filed: September 10, 2019
    Publication date: May 28, 2020
    Inventors: Jae-hyeon Jeon, Se-keun Park, Dong-sik Park, Seok-ho Shin
  • Patent number: 10665544
    Abstract: A semiconductor device includes a substrate including first and second regions, which are arranged along a first direction. A first conductive pattern extends in the first direction in the first region. A second conductive pattern extends in the first direction in the first region. The second conductive pattern is spaced apart from the first conductive pattern. A first spacer extends between the first conductive pattern and the second conductive pattern along a sidewall of the first conductive pattern, a sidewall of the second conductive pattern, and a boundary between the first and second regions. A distance between the first conductive pattern and the second region is smaller than a distance between the second conductive pattern and the second region.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: May 26, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Seok-Ho Shin
  • Publication number: 20190221535
    Abstract: A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a plurality of connection structures provided in a lower insulating layer of the edge region and arranged at first intervals in a first direction, an upper insulating layer covering the connection structures, and a plurality of redistribution pads disposed on the upper insulating layer and connected to the connection structures, respectively. Each of the redistribution pads includes a pad portion provided on the chip region. The pad portions of the redistribution pads are spaced apart from the connection structures by a first distance in a second direction intersecting the first direction when viewed in a plan view.
    Type: Application
    Filed: September 24, 2018
    Publication date: July 18, 2019
    Inventors: SEOK-HO SHIN, BONHWI GU, HYEKYEONG KWEON, SUNGJIN KIM, JOODONG KIM, JAEPIL LEE, DONGWON LIM
  • Publication number: 20190214345
    Abstract: A semiconductor device includes a substrate including first and second regions, which are arranged along a first direction. A first conductive pattern extends in the first direction in the first region. A second conductive pattern extends in the first direction in the first region. The second conductive pattern is spaced apart from the first conductive pattern. A first spacer extends between the first conductive pattern and the second conductive pattern along a sidewall of the first conductive pattern, a sidewall of the second conductive pattern, and a boundary between the first and second regions. A distance between the first conductive pattern and the second region is smaller than a distance between the second conductive pattern and the second region.
    Type: Application
    Filed: August 10, 2018
    Publication date: July 11, 2019
    Inventor: SEOK-HO SHIN
  • Patent number: 9761593
    Abstract: A semiconductor device includes: a substrate having a plurality of active regions; a plurality of bit lines extending in a first direction, the plurality of bit lines being separate from the substrate with an insulating layer therebetween; a plurality of first insulating lines extending in a second direction that is different from the first direction, wherein the plurality of first insulating lines intersect the plurality of bit lines and have upper surfaces having levels which are higher than those of upper surfaces of the plurality of bit lines relative to the substrate; and a plurality of first contact structures connected to the plurality of active regions, the plurality of first contact structures being disposed in an area defined by the plurality of bit lines and the plurality of first insulating lines.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: September 12, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-ho Shin
  • Patent number: 9590034
    Abstract: A method of forming fine patterns for a semiconductor device includes providing a substrate with a first region and a second region, forming a conductive layer on the substrate, the conductive layer including a plate portion covering the first region and first protruding portions extending from the plate portion in a first direction and covering a portion of the second region, forming first mask patterns on the conductive layer, the first mask patterns extending in the first direction and being spaced apart from each other in a second direction crossing the first direction, forming a second mask pattern on the second region to cover the first protruding portions, and patterning the conductive layer using the first and second mask patterns as an etch mask to form conductive patterns. In plan view, each of the first protruding portions is overlapped with a corresponding one of the first mask patterns.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: March 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-ho Shin, Chul Lee
  • Publication number: 20160329338
    Abstract: A semiconductor device includes: a substrate having a plurality of active regions; a plurality of bit lines extending in a first direction, the plurality of bit lines being separate from the substrate with an insulating layer therebetween; a plurality of first insulating lines extending in a second direction that is different from the first direction, wherein the plurality of first insulating lines intersect the plurality of bit lines and have upper surfaces having levels which are higher than those of upper surfaces of the plurality of bit lines relative to the substrate; and a plurality of first contact structures connected to the plurality of active regions, the plurality of first contact structures being disposed in an area defined by the plurality of bit lines and the plurality of first insulating lines.
    Type: Application
    Filed: July 19, 2016
    Publication date: November 10, 2016
    Inventor: Seok-ho Shin
  • Patent number: 9431324
    Abstract: A semiconductor device includes: a substrate having a plurality of active regions; a plurality of bit lines extending in a first direction, the plurality of bit lines being separate from the substrate with an insulating layer therebetween; a plurality of first insulating lines extending in a second direction that is different from the first direction, wherein the plurality of first insulating lines intersect the plurality of bit lines and have upper surfaces having levels which are higher than those of upper surfaces of the plurality of bit lines relative to the substrate; and a plurality of first contact structures connected to the plurality of active regions, the plurality of first contact structures being disposed in an area defined by the plurality of bit lines and the plurality of first insulating lines.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: August 30, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-ho Shin
  • Publication number: 20150371685
    Abstract: A method of forming fine patterns for a semiconductor device includes providing a substrate with a first region and a second region, forming a conductive layer on the substrate, the conductive layer including a plate portion covering the first region and first protruding portions extending from the plate portion in a first direction and covering a portion of the second region, forming first mask patterns on the conductive layer, the first mask patterns extending in the first direction and being spaced apart from each other in a second direction crossing the first direction, forming a second mask pattern on the second region to cover the first protruding portions, and patterning the conductive layer using the first and second mask patterns as an etch mask to form conductive patterns. In plan view, each of the first protruding portions is overlapped with a corresponding one of the first mask patterns.
    Type: Application
    Filed: April 9, 2015
    Publication date: December 24, 2015
    Inventors: Seok-ho Shin, Chul Lee
  • Publication number: 20150294923
    Abstract: A semiconductor device includes: a substrate having a plurality of active regions; a plurality of bit lines extending in a first direction, the plurality of bit lines being separate from the substrate with an insulating layer therebetween; a plurality of first insulating lines extending in a second direction that is different from the first direction, wherein the plurality of first insulating lines intersect the plurality of bit lines and have upper surfaces having levels which are higher than those of upper surfaces of the plurality of bit lines relative to the substrate; and a plurality of first contact structures connected to the plurality of active regions, the plurality of first contact structures being disposed in an area defined by the plurality of bit lines and the plurality of first insulating lines.
    Type: Application
    Filed: March 12, 2015
    Publication date: October 15, 2015
    Inventor: Seok-ho Shin
  • Publication number: 20120158187
    Abstract: An apparatus for adjusting a swivel angle of a display panel. The apparatus includes: a swivel frame configured to forwardly or reversely rotate in a first direction with respect to a reference surface; a panel mount bracket mounted on the swivel frame and allowing the display panel to be mounted thereon; a motor mounted on the swivel frame; and a driving force transmitting unit configured to receive a rotational force of the motor and drive the swivel frame to forwardly or reversely rotate, wherein the panel mount bracket is eccentrically disposed on a side of the swivel frame so that the display panel is spaced apart from the reference surface during rotation.
    Type: Application
    Filed: September 1, 2010
    Publication date: June 21, 2012
    Applicant: HUMAN ELECTRONICS CO., LTD.
    Inventor: Seok Ho Shin
  • Publication number: 20120067149
    Abstract: A slip control device including a shaft fixed to a reference surface; a first gear rotatably coupled to the shaft by a predetermined friction force with respect to an external circumferential surface of the shaft, for slipping with respect to the shaft when applied a rotation force greater than the predetermined friction force; a friction unit configured to provide the predetermined friction force between the first gear and the shaft; a rotation gear box for covering at least one surface of the first gear, coupled to a second gear to be rotated around the external circumferential surface of the shaft, and for rotating about the shaft during rotation of the second gear; and a motor disposed in the rotation gear box and providing the second gear with a rotation force to rotate the rotation gear box about the first gear.
    Type: Application
    Filed: May 18, 2010
    Publication date: March 22, 2012
    Inventors: Young Kwan Yoon, Seok Ho Shin