Patents by Inventor Seok-Hwan Moon
Seok-Hwan Moon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230027892Abstract: Provided is an electronic device including a plurality of substrate electrodes on a substrate, the substrate electrodes including initial electrodes and spare electrodes, a bonding material covering the initial electrodes and the spare electrodes, module structures respectively provided on first initial electrodes of the initial electrodes, and solders between each of the first initial electrodes and each of the module structures, wherein the spare electrodes include second spare electrodes, wherein the module structures are not provided on the second spare electrodes, wherein the bonding material on the first initial electrodes is harder than the bonding material on the second spare electrodes.Type: ApplicationFiled: July 14, 2022Publication date: January 26, 2023Applicant: Electronics and Telecommunications Research InstituteInventors: KWANG-SEONG CHOI, Yong-Sung EOM, Jiho JOO, GWANG-MUN CHOI, Seok-Hwan MOON, Ho-Gyeong YUN, CHANMI LEE, Ki-Seok JANG
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Publication number: 20220402070Abstract: Provided are a laser control structure and a laser bonding method using the same, and more particularly, a laser bonding method including: forming bonding portions on a substrate; providing a bonding object onto the bonding portions; providing a laser control structure onto the bonding object or the substrate; irradiating a laser toward the bonding object and the bonding portions; controlling quantity of laser light absorbed through the laser control structure; using the controlled quantity of laser light to heat the bonding portions and the bonding object to a bonding temperature; and bonding the bonding portions and the bonding object, wherein the laser control structure includes: a first substrate including a first region and a second region; a first thin film laminate on the first region; and a second thin film laminate on the second region, wherein: the first thin film laminate includes at least one first thin film layer and at least one second thin film layer, which are laminated on the first region; thType: ApplicationFiled: June 17, 2022Publication date: December 22, 2022Applicant: Electronics and Telecommunications Research InstituteInventors: Ki Seok JANG, Yong Sung EOM, GWANG-MUN CHOI, KWANG-SEONG CHOI, Jiho JOO, Seok-Hwan MOON, CHANMI LEE
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Publication number: 20220384674Abstract: Provided is a method for manufacturing an electronic device. The method for manufacturing the electronic device includes mapping good elements and defective elements on a substrate, providing a first transparent structure including a first adhesive layer on the substrate, selectively providing first laser light to the defective elements to cure the first adhesive layer on the defective elements and separate the defective elements from the substrate, providing a second transparent structure including a second adhesive layer, which adheres to new elements replaced for the defective elements, on the substrate, and selectively providing second laser light to the new elements to bond the new elements to the substrate.Type: ApplicationFiled: May 31, 2022Publication date: December 1, 2022Inventors: Jiho JOO, Yong Sung EOM, Kwang-Seong CHOI, Chanmi LEE, Gwang-Mun CHOI, Ki Seok JANG, Seok-Hwan MOON, Ho-Gyeong YUN
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Patent number: 11488841Abstract: Provided is a method for manufacturing a semiconductor package, the method including providing a semiconductor chip on a substrate, providing a bonding member between the substrate and the semiconductor chip, and bonding the semiconductor chip on the substrate by irradiating of a laser on the substrate. Here, the bonding member may include a thermosetting resin, a curing agent, and a laser absorbing agent.Type: GrantFiled: February 19, 2020Date of Patent: November 1, 2022Assignee: Electronics and Telecommunications Research InstituteInventors: Yong Sung Eom, Kwang-Seong Choi, Ki Seok Jang, Seok-Hwan Moon, Jiho Joo
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Publication number: 20220102603Abstract: Provided is a method of fabricating a semiconductor package. The method of fabricating the semiconductor package include preparing a lower element including a lower substrate, a lower electrode, an UBM layer, and a reducing agent layer, providing an upper element including an upper substrate, an upper electrode, and a solder bump layer, providing a pressing member on the upper substrate to press the upper substrate to the lower substrate, and providing a laser beam passing through the pressing member to bond the upper element to the lower element.Type: ApplicationFiled: August 11, 2021Publication date: March 31, 2022Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Kwang-Seong CHOI, Yong Sung EOM, Jiho JOO, Gwang-Mun CHOI, Seok-Hwan MOON, Chanmi LEE, Ki Seok JANG
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Publication number: 20210358885Abstract: Provides is a laser bonding method. The method includes forming a bonding part on a substrate; aligning a bonding target on the bonding part and bonding the bonding part and the bonding target. The bonding includes heating the bonding part using a laser. The bonding part formed on the substrate includes an adhesive layer and a conductive particle located in the adhesive layer.Type: ApplicationFiled: July 28, 2021Publication date: November 18, 2021Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Kwang-Seong CHOI, Yong Sung EOM, KeonSoo JANG, Seok-Hwan MOON, Hyun-cheol BAE
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Patent number: 11107790Abstract: A laser bonding method includes forming a bonding part including an adhesive layer and a conductive particle disposed within the adhesive layer on a substrate; aligning a bonding target by disposing the bonding target on a surface of the bonding part opposite the substrate; disposing a pressing part on a surface of the bonding target that is opposite to the bonding part and pressing the bonding target onto the bonding part through the pressing part; heating the bonding target by irradiating at least the pressing part with a laser and conducting heat from the pressing part to the bonding target and from the bonding target to the bonding part; and bonding together the bonding part and the bonding target by the heat conducted from the bonding target to the bonding part so that the conductive particle electrically connects the substrate and the bonding target. The pressing part may be removed.Type: GrantFiled: August 29, 2019Date of Patent: August 31, 2021Assignee: Electronics and Telecommunications Research InstituteInventors: Kwang-Seong Choi, Yong Sung Eom, KeonSoo Jang, Seok-Hwan Moon, Hyun-cheol Bae
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Publication number: 20210252620Abstract: The present disclosure relates to a transfer and bonding method using a laser. As a plurality of devices or packages are simultaneously transferred onto a substrate from a transfer tape by irradiating a top surface of the transfer tape with a first laser, and the plurality of transferred devices or packages are simultaneously bonded to pads of a substrate by irradiating a top surface of the devices or packages with a second laser, a speed of a transfer and bonding process may be extremely maximized.Type: ApplicationFiled: February 18, 2021Publication date: August 19, 2021Applicant: Electronics and Telecommunications Research InstituteInventors: KWANG-SEONG CHOI, Yong Sung EOM, Jiho JOO, Seok-Hwan MOON, Ho-Gyeong YUN, Ki Seok JANG, GWANG-MUN CHOI
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Publication number: 20200266078Abstract: Provided is a method for manufacturing a semiconductor package, the method including providing a semiconductor chip on a substrate, providing a bonding member between the substrate and the semiconductor chip, and bonding the semiconductor chip on the substrate by irradiating of a laser on the substrate. Here, the bonding member may include a thermosetting resin, a curing agent, and a laser absorbing agent.Type: ApplicationFiled: February 19, 2020Publication date: August 20, 2020Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Yong Sung EOM, KWANG-SEONG CHOI, Ki Seok JANG, Seok-Hwan MOON, Jiho JOO
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Patent number: 10636761Abstract: Provided is a method of fabricating a semiconductor package. The method includes preparing a package substrate having a substrate pad, and mounting a semiconductor chip on the substrate pad. Mounting the semiconductor chip includes forming a resin layer containing a solder and reducing agent granules having a first capsule layer, between a chip pad of the semiconductor chip and the substrate pad, and bonding the chip pad to the substrate pad using laser irradiated to the semiconductor chip.Type: GrantFiled: August 28, 2018Date of Patent: April 28, 2020Assignee: Electronics and Telecommunications Reearch InstituteInventors: Kwang-Seong Choi, Yong-Sung Eom, Keon-Soo Jang, Seok Hwan Moon, Hyun-Cheol Bae, Ieeseul Jeong, Wagno Alves Braganca Junior
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Publication number: 20200075535Abstract: Provides is a laser bonding method. The method includes forming a bonding part on a substrate; aligning a bonding target on the bonding part and bonding the bonding part and the bonding target. The bonding includes heating the bonding part using a laser. The bonding part formed on the substrate includes an adhesive layer and a conductive particle located in the adhesive layer.Type: ApplicationFiled: August 29, 2019Publication date: March 5, 2020Applicant: Electronics and Telecommunications Research InstituteInventors: Kwang-Seong CHOI, Yong Sung EOM, KeonSoo JANG, Seok-Hwan MOON, Hyun-cheol BAE
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Publication number: 20190287870Abstract: The inventive concept relates to a filling composition for a semiconductor package. The filling composition for a semiconductor package may include a resin, a curing agent, and an insulating filler. The insulating filler may include a first filler body part, a second filler body part, a polymer chain coupled to the first filler body part and the second filler body part, and supramolecules coupled to the polymer chain.Type: ApplicationFiled: March 18, 2019Publication date: September 19, 2019Applicant: Electronics and Telecommunications Research InstituteInventors: KeonSoo JANG, Yong Sung EOM, KWANG-SEONG CHOI, Seok-Hwan MOON, Hyun-cheol BAE
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Publication number: 20190211231Abstract: Provided are an adhesive film, and a method of fabricating a semiconductor package using the same. The adhesive film includes a thermoplastic resin containing a hydroxyl group, a thermosetting resin, and an anhydride.Type: ApplicationFiled: December 14, 2018Publication date: July 11, 2019Inventors: KeonSoo JANG, Yong Sung EOM, Kwang-Seong CHOI, Seok-Hwan MOON, Hyun-cheol BAE
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Publication number: 20190067235Abstract: Provided is a method of fabricating a semiconductor package. The method includes preparing a package substrate having a substrate pad, and mounting a semiconductor chip on the substrate pad. Mounting the semiconductor chip includes forming a resin layer containing a solder and reducing agent granules having a first capsule layer, between a chip pad of the semiconductor chip and the substrate pad, and bonding the chip pad to the substrate pad using laser irradiated to the semiconductor chip.Type: ApplicationFiled: August 28, 2018Publication date: February 28, 2019Applicant: Electronics and Telecommunications Research InstituteInventors: Kwang-Seong CHOI, Yong-Sung Eom, Keon-Soo Jang, Seok Hwan Moon, Hyun-Cheol Bae, leeseul Jeong, Wagno Alves Braganca Junior
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Patent number: 10020201Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.Type: GrantFiled: April 8, 2016Date of Patent: July 10, 2018Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Chi Hoon Jun, Sang Choon Ko, Seok-Hwan Moon, Woojin Chang, Sung-Bum Bae, Young Rak Park, Je Ho Na, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20160225631Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.Type: ApplicationFiled: April 8, 2016Publication date: August 4, 2016Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Chi Hoon JUN, Sang Choon KO, Seok-Hwan MOON, Woojin CHANG, Sung-Bum BAE, Young Rak PARK, Je Ho NA, Jae Kyoung MUN, Eun Soo NAM
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Patent number: 9337121Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.Type: GrantFiled: July 7, 2014Date of Patent: May 10, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Chi Hoon Jun, Sang Choon Ko, Seok-Hwan Moon, Woojin Chang, Sung-Bum Bae, Young Rak Park, Je Ho Na, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 9296205Abstract: Provided are a large-area nano-scale active printing device, a fabricating method of the same, and a printing method using the same. The printing device may include a substrate, first interconnection lines extending along a first direction, on the substrate, an interlayered dielectric layer provided on the first interconnection lines to have holes partially exposing the first interconnection lines, second interconnection lines provided adjacent to the holes in the interlayered dielectric layer to cross the first interconnection lines, and wedge-shaped electrodes provided at intersections with the first and second interconnection lines and connected to the first interconnection lines. The wedge-shaped electrodes protrude upward at centers of the holes.Type: GrantFiled: June 12, 2015Date of Patent: March 29, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Yong Suk Yang, In-Kyu You, Soon-Won Jung, Bock Soon Na, Seok-Hwan Moon
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Publication number: 20150348802Abstract: A method for fabricating a thinned flat plate heat pipe, including forming a body part having a flat plate shape by using an extrusion process, forming a through-hole in the longitudinal direction of the body part, and forming one or more grooves on at least one side of an inner wall of the through-hole to allow a working fluid to flow.Type: ApplicationFiled: August 13, 2015Publication date: December 3, 2015Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventor: Seok Hwan MOON
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Patent number: 9179577Abstract: Disclosed are a flat heat pipe which has a structure integrated with a heat sink, and a facilitated fabrication method thereof. The flat heat pipe includes: a flat body portion including a plurality of heat sink fins formed on an outer surface thereof, and a plurality of through-holes formed therein and being separated by at least one separation film; and at least one groove formed in at least one surface from among a top surface and a bottom surface of one side portion of each of the plurality of through-holes.Type: GrantFiled: August 10, 2012Date of Patent: November 3, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventor: Seok Hwan Moon