Abstract: In accordance with an embodiment of the present disclosure, an operating method of a controller for controlling a nonvolatile memory device may include: generating pre-read information based on a first read request, reading out 1st sub-chunks respectively included in a plurality of data chunks from the nonvolatile memory device, and providing a host with the read 1st sub-chunks, wherein the first read request includes respective addresses of the 1st sub-chunks; starting, after the 1st sub-chunks are provided to the host, a pre-read operation of reading out 2nd sub-chunks respectively included in the plurality of data chunks from the nonvolatile memory device based on the pre-read information and storing the read 2nd sub-chunks into a memory in the controller; and providing, after the pre-read operation is started, the host with the 2nd sub-chunks stored in the memory in response to a second read request received from the host.

Abstract: A memory system includes a memory device including first memory blocks each including a memory cell storing a 1-bit data, and second memory blocks each including a memory cell storing a multi-bit data. The memory system further includes a controller configured to estimate data input/output speed of an operation requested by an external device and to determine, based on the estimated data input/output speed, a buffering ratio of pieces of buffered data, temporarily stored in the first memory blocks, to pieces of inputted data. The controller uses the buffer ratio to determine whether to program pieces of inputted data into the second memory blocks directly or to buffer the inputted data in the first memory blocks before programming it into the second memory blocks.

Abstract: A data storage device may include a controller configured to generate an ID based on a name and a version of an application transmitted from a host device together with a logic address, and generate an L2P map list for each application based on the ID; and a nonvolatile memory apparatus including a plurality of map blocks configured to store map data for each ID.

Abstract: Provided is a method for generating a one class model based on a data frequency. The method for generating a one class model based on a data frequency includes: generating, by a machine learning apparatus, a plurality of spatial coordinates by arranging a plurality of learning data in corresponding coordinates in a feature space; classifying, by the machine learning apparatus, the plurality of spatial coordinates into a plurality of internal coordinates PI and a plurality of external coordinates PO based on a frequency of the learning data arranged in the respective spatial coordinates which belong to the plurality of spatial coordinates; and generating, by the machine learning apparatus, a one class model based on the plurality of internal coordinates PI based on mutual spatial distances of the plurality of external coordinates PO and the plurality of internal coordinates PI.

Abstract: A method to map a plurality of feature maps of a neural network onto a memory hierarchy includes mapping a first feature map of the plurality of feature maps to a memory in a memory hierarchy having available memory space and providing quickest access to the first feature map. The method also includes, when the first feature map expires, removing the first feature map from the memory used to store the first feature map.

Abstract: Provided herein is a memory controller and a method of operating the same. A memory controller for controlling a memory device including a plurality of memory blocks may include a workload determiner and a write controller. The workload determiner is configured to set a threshold number of free blocks for determining whether a number of free blocks, among the plurality of memory blocks, falls within a normal range based on a predicted idle period of the memory device, and to determine a workload pattern of the memory device by comparing the number of free blocks with the threshold number of free blocks. The write controller is configured to control the memory device so that one of a fast write operation and a normal write operation is selectively performed depending on the workload pattern.

Abstract: There are provided a memory controller for managing meta data and an operating method of the memory controller. The memory controller includes: a buffer memory for storing meta data used to control an operation of a memory device; and a central processing unit for updating the meta data stored in the buffer memory whenever the operation of the memory device is controlled. The central processing unit may transmit the meta data stored in the buffer memory to a host at a first frequency, and transmit the meta data stored in the buffer memory to the memory device at a second frequency lower than the first frequency.

Abstract: A memory system includes a memory device including memory blocks and a memory controller configured to control the memory device. The memory device stores a firmware which includes binaries, and the binaries include a first binary and a second binary. The memory controller loads the firmware to a first region in a working memory, loads the first binary to a second region which is included in the first region, and loads the second binary to a third region which is included in the first region and is different from the second region. The memory controller stores information on an entry function corresponding to a target function included in the second binary, in a fourth region which is different from the first region. A start address of the second region is determined as a fixed value, and a start address of the third region is dynamically determined.

Abstract: A switch control apparatus capable of effectively controlling a switch during a process of controlling the switch provided in a battery pack. When the switch is shifted from a closed state to an open state, the current caused by the generated counter electromotive force is quickly released, thereby quickly shifting the switch to turn on or off. In addition, since the voltage applied to the control unit falls within the rated voltage range, the stability of the switch control circuit may be enhanced.

Abstract: A data storage device includes a nonvolatile memory device including a plurality of memory groups, each of which includes a plurality of memory regions in interleaving units and a controller configured to determine and manage interleaving-aware dirty (IAD) of a write-requested logical address whenever write-requested data is written in the nonvolatile memory device, and select a victim memory group among the plurality of memory groups using the interleaving-aware dirty.

Abstract: The present disclosure relates to an electronic device. A memory controller having improved read interleaving and write interleaving performance may include a buffer memory temporarily storing data chunks read from a sacrificial area, a target die information manager generating target die information on a plurality of memory dies in which the data chunks are respectively stored according to logical address counts of the data chunks corresponding to the plurality of memory dies, respectively, determined based on correspondence information between the plurality of memory dies and logical addresses provided from a host, and a write operation controller controlling the plurality of memory dies so that the data chunks temporarily stored in the buffer memory are stored in the plurality of memory dies on the basis of the target die information.

Abstract: An electronic device includes a memory controller selecting map data to be output to a host. The memory controller includes an address counter and a map data selector. The address counter counts a number of times a logical block address corresponding to a request is received based on the request received from the host and outputs an activation signal indicating that an index to which the logical block address belongs is an activation index when an activation count corresponding to the index is equal to or greater than a preset value, the activation count being generated based on a counting result. The map data selector selects map data to be output to the host based on the activation signal. The address counter decreases the activation count by a preset size when a size of the selected map data exceeds a storage capacity of the host allocated for storing map data.

Abstract: A memory includes a memory device including plural memory blocks, each memory block including plural pages, and a controller coupled to the memory device and configured to select a target memory block among the plural memory blocks, the target memory block including a first page to an N page (N is a positive integer), and program data in the target memory block, based on a type of the data, either in a first direction from the first page to the N page or in a second direction from the N page to the first page.

Abstract: Disclosed is a switch control apparatus capable of effectively controlling a switch during a process of controlling the switch provided in a battery pack. When the switch is shifted from a closed state to an open state, the current caused by the generated counter electromotive force is quickly released, thereby quickly shifting the switch to turn on or off. In addition, since the voltage applied to the control unit falls within the rated voltage range, the stability of the switch control circuit may be enhanced.

Abstract: A memory system comprising: a memory device including a plurality of memory blocks; and a controller suitable for: periodically generating, based on system information periodically inputted from a host, performance information indicating whether an internal operation to be performed on the plurality of memory blocks without a command inputted from the host is performable; accumulatively storing the generated performance information; determining whether the internal operation is performable within a period subsequent to a current period based on the accumulated performance information; and performing the internal operation on the memory blocks during the subsequent period according to a result of the determination.

Abstract: A memory system may include: a non-volatile memory device suitable for storing firmware; a volatile memory device comprising a write cache region for temporarily storing write data to be programmed into the non-volatile memory device and a firmware cache region for loading the firmware from the non-volatile memory device; and a controller suitable for: moving, to the write cache region, changeable firmware data that is generated or modified in the firmware cache region during an operation of the controller; programming the changeable firmware data, after it is moved into the write cache region, into the non-volatile memory device; and generating, in the firmware cache region, access information of the changeable firmware data.

Abstract: Provided herein may be a storage device, a method of operating the storage device, a computing system including the storage device and a host device for controlling the storage device, and a method of operating the computing system. A memory device may include a host interface configured to receive bad block information on one or more bad blocks of a second memory device from a host device; and a bad block processor configured to store data of one or more source bad blocks of the first memory device in one or more available memory blocks of the first memory device by controlling the first memory device, the source bad blocks of the first memory device corresponding to the bad block information, the available memory blocks being different from the source bad blocks.

Abstract: The present disclosure relates to an electronic device. A memory controller having improved read interleaving and write interleaving performance may include a buffer memory temporarily storing data chunks read from a sacrificial area, a target die information manager generating target die information on a plurality of memory dies in which the data chunks are respectively stored according to logical address counts of the data chunks corresponding to the plurality of memory dies, respectively, determined based on correspondence information between the plurality of memory dies and logical addresses provided from a host, and a write operation controller controlling the plurality of memory dies so that the data chunks temporarily stored in the buffer memory are stored in the plurality of memory dies on the basis of the target die information.

Abstract: A data storage device may include a controller configured to generate an ID based on a name and a version of an application transmitted from a host device together with a logic address, and generate an L2P map list for each application based on the ID; and a nonvolatile memory apparatus including a plurality of map blocks configured to store map data for each ID.

Abstract: A data storage device may include: a nonvolatile memory configured to store L2P (Logical to Physical) map data and user data; and a controller configured to determine whether read commands which are sequentially transferred from a host device correspond to a backward sequential read, increase a backward sequential read count when the read commands are backward sequential read, set a pre-read start logical block address (LBA) and a length according to a preset condition, when the backward sequential read count is equal to or greater than a reference value, and load an L2P map of the corresponding LBA and user data corresponding to the L2P map from the nonvolatile memory in advance.