Patents by Inventor Seok-Jun Lee
Seok-Jun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8230313Abstract: In at least some disclosed embodiments, a system includes a Viterbi decoder and predecoding logic coupled to the Viterbi decoder. The predecoding logic decodes encoded data. The system further includes detection logic coupled to the predecoding logic. The detection logic tests decoded data, and the detection logic produces a binary result. The Viterbi decoder is enabled if the binary result is a first value, and the Viterbi decoder is disabled if the binary result is a second value.Type: GrantFiled: August 10, 2009Date of Patent: July 24, 2012Assignee: Texas Instruments IncorporatedInventors: Rami Abdallah, Seok-Jun Lee, Manish Goel
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Patent number: 8205145Abstract: A high speed add-compare-select (ACS) circuit for a Viterbi decoder or a turbo decoder has a lower critical path delay than that achievable using a traditional ACS circuit. According to one embodiment of the invention, the path and branch metrics are split into most-significant and least-significant portions, such portions separately added in order to reduce the propagation delay.Type: GrantFiled: November 5, 2008Date of Patent: June 19, 2012Assignee: Texas Instruments IncorporatedInventors: Seok-Jun Lee, Yuming Zhu, Manish Goel
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Patent number: 8099658Abstract: A Viterbi decoder includes a branch metric unit, an add-compare select unit coupled to the branch metric unit, and a trace-back unit coupled to the add-compare select unit. The branch metric unit includes a branch metric computation unit coupled to a thresholder unit. The branch metric computation unit is configured to compute a branch metric. The thresholder unit is configured to compare the branch metric with a threshold value. If the branch metric is greater than the threshold value, the thresholder unit is configured to forward the threshold value to the add-compare select and not forward the branch metric to the add-compare select unit. Implementing such a branch metric ceiling allows for a predictable reduction in the significant bits of calculations in the Viterbi decoder, which allows for reduction of complexity via elimination of gates and storage elements.Type: GrantFiled: October 31, 2007Date of Patent: January 17, 2012Assignee: Texas Instruments IncorporatedInventors: Seok-Jun Lee, Srinivas Lingam, Anuj Batra, Manish Goel
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Patent number: 8059745Abstract: A receiver system for receiving and decoding modulated communications signals in a multiple-input, multiple-output (MIMO) environment, where the signals are modulated according to Orthogonal Frequency Division Modulation (OFDM). The receiver system includes shared decoder logic circuitry that executes a maximum-likelihood (ML) estimation algorithm in deriving the signals transmitted from the multiple transmitting antennae, as those signals were received over all of the receiving antennae. For a control channel portion of the data frame, the shared decoder logic circuitry applies Viterbi decoding to the transmitted datastreams estimated by the ML estimation algorithm. This sharing of decoder logic reduces the integrated circuit chip area, and also power dissipation, otherwise required in performing these complex decoding functions.Type: GrantFiled: August 6, 2008Date of Patent: November 15, 2011Assignee: Texas Instruments IncorporatedInventors: Seok-Jun Lee, Manish Goel
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Publication number: 20110055668Abstract: A method of determining positions of one or more error bits is disclosed. The method includes receiving a BCH codeword at input circuitry of a decoder device, establishing a threshold number of correctable bits, and determining from the received BCH codeword and a root of an encoder polynomial, a value of each of one or more syndromes. The number of the one or more syndromes is twice a maximum number of correctable bits in the received BCH codeword. When the maximum number of correctable bits in the received BCH codeword is less than the threshold number of correctable bits, the value of each coefficient in a scaled error locator polynomial is determined by performing a non-iterative, closed-form solution on the scaled error locator polynomial. The scaled error locator polynomial is an original error locator polynomial scaled by a constant scale factor. The constant scale factor is determined according to the value of each of the one or more syndromes.Type: ApplicationFiled: July 29, 2010Publication date: March 3, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Hun-Seok Kim, Seok-Jun Lee, Manish Goel
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Publication number: 20110055643Abstract: A communication system includes a receiver configured to receive a packet that contains plural codewords, and a codeword failure detector cooperatively operable with the receiver. The codeword failure detector can be configured to detect a codeword failure in at least one codeword of the plural codewords as it is being received by the receiver, and to terminate reception at the receiver, when the codeword failure is detected before the end of the packet, to put the receiver into a power save mode for a duration of a remainder of the packet that contains the at least one codeword.Type: ApplicationFiled: July 29, 2010Publication date: March 3, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Hun-Seok KIM, Seok-Jun LEE, Anuj BATRA, Manish GOEL
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Patent number: 7889807Abstract: In some embodiments, a device includes a multiple-input multiple-output (“MIMO”) decoder module coupled to a first log-likelihood-ratio (“LLR”) computing unit. The decoder module includes at least one processing unit and at least one sorting unit. The decoder module preferably uses a K-best breadth-first search method to decode data from MIMO sources. In some embodiments, a method includes receiving data representing a vector of receive signal samples detected by multiple receive transceivers. The method further includes performing a K-best breadth-first search on the data to obtain an estimated constellation point. The method further includes providing a user data stream based at least in part on the estimated constellation point.Type: GrantFiled: May 31, 2007Date of Patent: February 15, 2011Assignee: Texas Instruments IncorporatedInventors: Hun-Seok Kim, Seok-Jun Lee, Manish Goel
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Publication number: 20100034321Abstract: A receiver system for receiving and decoding modulated communications signals in a multiple-input, multiple-output (MIMO) environment, where the signals are modulated according to Orthogonal Frequency Division Modulation (OFDM). The receiver system includes shared decoder logic circuitry that executes a maximum-likelihood (ML) estimation algorithm in deriving the signals transmitted from the multiple transmitting antennae, as those signals were received over all of the receiving antennae. For a control channel portion of the data frame, the shared decoder logic circuitry applies Viterbi decoding to the transmitted datastreams estimated by the ML estimation algorithm. This sharing of decoder logic reduces the integrated circuit chip area, and also power dissipation, otherwise required in performing these complex decoding functions.Type: ApplicationFiled: August 6, 2008Publication date: February 11, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Seok-Jun Lee, Manish Goel
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Publication number: 20100034324Abstract: A system includes a Viterbi decoder. The Viterbi decoder includes add compare select logic. The add compare select logic determines path metrics for an encoded signal. The add compare select logic also is shared to determine a best state by which trace-back procedure gets started, resulting in hardware saving.Type: ApplicationFiled: August 10, 2009Publication date: February 11, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Rami ABDALLAH, Seok-Jun LEE, Manish GOEL
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Publication number: 20100034325Abstract: In at least some disclosed embodiments, a system includes a Viterbi decoder and predecoding logic coupled to the Viterbi decoder. The predecoding logic decodes encoded data. The system further includes detection logic coupled to the predecoding logic. The detection logic tests decoded data, and the detection logic produces a binary result. The Viterbi decoder is enabled if the binary result is a first value, and the Viterbi decoder is disabled if the binary result is a second value.Type: ApplicationFiled: August 10, 2009Publication date: February 11, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Rami Abdallah, Seok-Jun Lee, Manish Goel
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Publication number: 20090313399Abstract: A system and method for using a direct memory access (“DMA”) channel to reorganize data during transfer from one device to another are disclosed herein. A DMA channel includes demultiplexing logic and multiplexing logic. The demultiplexing logic is configurable to distribute each data value read into the DMA channel to a different one of a plurality of data streams than an immediately preceding value. The multiplexing logic is configurable to select a given one of the plurality of data streams. The DMA channel is configurable to write a value from the given data stream to a storage location external to the DMA channel.Type: ApplicationFiled: June 5, 2009Publication date: December 17, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Srinivas LINGAM, Seok-Jun LEE
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Publication number: 20090274200Abstract: A system and method for time domain interpolation of signals for channel estimation. A method for computing channel estimates comprises storing symbols in a buffer, using time domain interpolation (TDI) for a first time to compute channel estimates for a set of sub-carriers of a symbol. The channel estimates are computed from the symbol and a first number of required symbols in the buffer. The method also comprises using TDI for a second time to compute channel estimates for the set of sub-carriers of a symbol. The channel estimates are computed from the symbol, a second number of required symbols in the buffer, and a buffered symbol used as a missing required symbol if the missing required symbol is not in the buffer.Type: ApplicationFiled: May 5, 2008Publication date: November 5, 2009Inventors: Muhammad Zubair Ikram, Seok-Jun Lee, Murtaza Ali
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Publication number: 20090110126Abstract: A Viterbi decoder includes a branch metric unit, an add-compare select unit coupled to the branch metric unit, and a trace-back unit coupled to the add-compare select unit. The branch metric unit includes a branch metric computation unit coupled to a thresholder unit. The branch metric computation unit is configured to compute a branch metric. The thresholder unit is configured to compare the branch metric with a threshold value. If the branch metric is greater than the threshold value, the thresholder unit is configured to forward the threshold value to the add-compare select and not forward the branch metric to the add-compare select unit. Implementing such a branch metric ceiling allows for a predictable reduction in the significant bits of calculations in the Viterbi decoder, which allows for reduction of complexity via elimination of gates and storage elements.Type: ApplicationFiled: October 31, 2007Publication date: April 30, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Seok-Jun LEE, Srinivas LINGAM, Anuj BATRA, Manish GOEL
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Publication number: 20090089556Abstract: A high speed add-compare-select (ACS) circuit for a Viterbi decoder or a turbo decoder has a lower critical path delay than that achievable using a traditional ACS circuit. According to one embodiment of the invention, the path and branch metrics are split into most-significant and least-significant portions, such portions separately added in order to reduce the propagation delay.Type: ApplicationFiled: November 5, 2008Publication date: April 2, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Seok-Jun Lee, Yuming Zhu, Manish Goel
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Publication number: 20080298493Abstract: The problem outlined above may at least in part be addressed by N-Candidate Depth-First Decoding methods and systems that employ such methods. In some embodiments, the method includes receiving data representing a vector of receive signals detected by multiple receive transceivers; performing an N-candidate, depth-first search on the data to obtain an estimated constellation point; and providing a user data stream based at least in part on the estimated constellation point. In some embodiments the system includes a multiple-input multiple-output decoder. The decoder is configured to perform an N-candidate, depth-first search as part of converting a receive signal into a data stream.Type: ApplicationFiled: May 31, 2007Publication date: December 4, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Hun-Seok KIM, Seok-Jun LEE, Manish GOEL
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Publication number: 20080298478Abstract: In some embodiments, a device includes a multiple-input multiple-output (“MIMO”) decoder module coupled to a first log-likelihood-ratio (“LLR”) computing unit. The decoder module includes at least one processing unit and at least one sorting unit. The decoder module preferably uses a K-best breadth-first search method to decode data from MIMO sources. In some embodiments, a method includes receiving data representing a vector of receive signal samples detected by multiple receive transceivers. The method further includes performing a K-best breadth-first search on the data to obtain an estimated constellation point. The method further includes providing a user data stream based at least in part on the estimated constellation point.Type: ApplicationFiled: May 31, 2007Publication date: December 4, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Hun-Seok KIM, Seok-Jun LEE, Manish GOEL
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Patent number: 7324614Abstract: A branch metric duplication method substantially reduces interconnection delays. The branch metric duplication method is particularly useful to implement a high speed radix-4 Viterbi decoder targeted for FPGA applications. The decoder includes a plurality of branch metric computation units (BMCUs), at least one add-compare-select unit (ACSU) having a plurality of cells, and a survivor path memory unit (SMU). The plurality of BMCUs, the at least one ACSU, and the SMU are configured to implement the decoder.Type: GrantFiled: December 18, 2002Date of Patent: January 29, 2008Assignee: Texas Instruments IncorporatedInventors: Seok-Jun Lee, Manish Goel
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Publication number: 20070140292Abstract: A methods and apparatus for synchronizing a de-interleaver are disclosed. One example method includes fixing a phase of a de-interleaver in a first state; de-interleaving symbols in the signal while the phase of the de-interleaver is in the first state; processing the de-interleaved symbols; detecting if the known information is present in the processed de-interleaved symbols; and switching the phase of the de-interleaver between the first state and a second state when the known information is detected in the processed de-interleaved symbols.Type: ApplicationFiled: December 17, 2005Publication date: June 21, 2007Inventors: Charles Sestok, Seok-Jun Lee, Manish Goel
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Publication number: 20070113161Abstract: A Viterbi decoder includes a branch metric unit for generating branch metrics between two states at two different time periods, a traceback unit, a traceback memory and an add-compare-select circuit. The add-compare-select circuit includes a plurality of cascaded add-compare-select sub-circuits, each add-compare-select sub-circuit calculating a path metric responsive to a plurality of branch metrics from the branch metric unit and a plurality of pre-calculated path metrics, where at least one of the add-compare-select sub-circuits receives a set of pre-calculated path metrics from another one of the add-compare-select sub-circuits.Type: ApplicationFiled: November 7, 2006Publication date: May 17, 2007Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Srinivas Lingam, Seok-Jun Lee, Anuj Batra, Manish Goel
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Patent number: 6993702Abstract: A de-interleaver-de-puncturer architecture is scalable and capable of achieving a higher data throughput than that achievable using a conventional disjointed de-interleaver-de-puncturer architecture. The higher data throughput is achieved without increasing the clock speed of the de-interleaver. The scalable de-interleaver-de-puncturer architecture is also less complex than a conventional disjointed de-interleaver-de-puncturer architecture.Type: GrantFiled: December 18, 2002Date of Patent: January 31, 2006Assignee: Texas Instruments IncorporatedInventors: Seok-Jun Lee, Manish Goel