Patents by Inventor Seok-Jun Won

Seok-Jun Won has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7294546
    Abstract: A capacitor includes an upper electrode formed by physical vapor deposition and chemical vapor deposition. The upper electrode of the capacitor may include a first upper electrode formed by chemical vapor deposition and a second upper electrode formed by physical vapor deposition. Alternatively, the upper electrode may include a first upper electrode formed by physical vapor deposition and a second upper electrode formed by chemical vapor deposition. The upper electrode of the capacitor is formed through two steps using chemical vapor deposition and physical vapor deposition. Therefore, the upper electrode can be thick and rapidly formed, whereby electrical characteristics of the upper electrode are not deteriorated.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: November 13, 2007
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Hong-Ki Kim, Ho-Kyu Kang, Moon-Han Park, Myong-Geun Yoon, Seok-Jun Won, Yong-Kuk Jeong, Kyung-Hun Kim
  • Patent number: 7288453
    Abstract: There is provided a method of fabricating an analog capacitor using a post-treatment technique. The method includes forming a lower insulating layer on a semiconductor substrate. A bottom electrode is formed on the lower insulating layer, and a capacitor dielectric layer is formed on the bottom electrode. Then, the capacitor dielectric layer is post-treated in a deoxidizing medium. Then, the post-treated capacitor dielectric layer is post-treated in an oxidizing medium. A top electrode is formed on the post-treated capacitor dielectric layer. The analog capacitor fabricated through the post-treatment as above has a low VCC.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: October 30, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Kuk Jeong, Seok-Jun Won, Dae-Jin Kwon
  • Patent number: 7271038
    Abstract: A ruthenium (Ru) film is formed on a substrate as part of a two-stage methodology. During the first stage, the Ru film is formed on the substrate in a manner in which the Ru nucleation rate is greater than the Ru growth rate. During the second stage, the Ru film is formed on the substrate in a manner in which the Ru growth rate is greater than the Ru nucleation rate.
    Type: Grant
    Filed: March 15, 2004
    Date of Patent: September 18, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-jun Won, Cha-young Yoo
  • Publication number: 20070210409
    Abstract: A semiconductor device having improved capacitance may include a semiconductor substrate, a gate electrode on the semiconductor substrate, a capacitor lower electrode formed of substantially the same material as the gate electrode and being in the same layer as the gate electrode, an interlayer insulating film that covers the gate electrode and capacitor lower electrode, the interlayer insulating film including an opening through which the top surface of the capacitor lower electrode may be exposed, a capacitor upper electrode that fills the opening, and a dielectric film between the capacitor lower electrode and capacitor upper electrode.
    Type: Application
    Filed: February 28, 2007
    Publication date: September 13, 2007
    Inventors: Seok jun Won, Jung-min Park
  • Publication number: 20070186857
    Abstract: Example embodiments relate to an apparatus and method for manufacturing a semiconductor device. Other example embodiments relate to a plasma processing apparatus having an in-situ cleaning function and a method of using the same. The plasma processing apparatus may include an outer chamber, an inner chamber installed in the outer chamber, a gas supply unit for supplying a process gas or a cleaning gas into the inner chamber, an electrode positioned in the inner chamber, an electrode plasma power supply for applying power to the electrode, a first flexible member connecting the inner chamber and the outer chamber and having a first connector therein electrically connected to the inner chamber and/or a first chamber plasma power supply connected to the first connector and applying power to the inner chamber through the first connector.
    Type: Application
    Filed: February 1, 2007
    Publication date: August 16, 2007
    Inventors: Ju-Youn Kim, Seok-Jun Won, Weon-Hong Kim
  • Publication number: 20070178249
    Abstract: Provided is a method of forming a metal layer using metal-organic chemical vapor deposition (MOCVD). The method includes using MOCVD to form on a dielectric layer a metal layer having a first thickness, performing a first plasma process on the metal layer, using the MOCVD process to form a metal layer having a second thickness on the metal layer having the first thickness and performing a second plasma process on the metal layer having the second thickness, wherein the second plasma process has an energy level greater than the energy level of the first plasma process.
    Type: Application
    Filed: January 17, 2007
    Publication date: August 2, 2007
    Inventors: Min-Woo Song, Seok-Jun Won, Dae-Jin Kwon, Weon-Hong Kim, Ju-Youn Kim, Jung-Min Park
  • Publication number: 20070175495
    Abstract: An apparatus for treating plasma includes an inner chamber, an outer chamber receiving the inner chamber and including a gas supplier that supplies a gas into the inner chamber, an inner electrode disposed in the inner chamber, and a plasma generator supplying power independently to the inner electrode and the inner chamber.
    Type: Application
    Filed: January 30, 2007
    Publication date: August 2, 2007
    Inventors: Weon-Hong Kim, Seok-Jun Won, Dae-Jin Kwon, Min-Woo Song, Ju-Youn Kim, Jung-Min Park
  • Publication number: 20070169697
    Abstract: In a method of manufacturing a capacitor of a semiconductor device and an apparatus therefor, dielectric layers are deposited using only a source gas without a reactant gas and a curing process is performed a single time. As a result, process simplification, yield improvement, and equipment simplification are achieved. In a stand-alone memory or an embedded memory, the step coverage is enhanced and oxidation of a storage node contact plug is prevented. Also, in an analog capacitor, an RF capacitor, or a high-voltage capacitor, which uses thicker dielectric layers than the stand-alone capacitor or the embedded capacitor, the manufacturing process is greatly simplified.
    Type: Application
    Filed: February 23, 2007
    Publication date: July 26, 2007
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yong-kuk Jeong, Myong-geun Yoon, Seok-jun Won, Dae-jin Kwon
  • Publication number: 20070166913
    Abstract: There is provided a method of forming a semiconductor device. A dielectric layer including a metal (e.g., a gate insulating layer and/or a tunnel insulating layer) may be formed on a substrate, and a metal nitride layer containing more metal component than nitrogen may be formed on the dielectric layer by PEALD. The metal nitride layer may be formed by alternately supplying a metal source including the metal and an NH3 gas, and providing plasma during a supplying of the NH3 gas. Because a material included in the dielectric layer and that included in the electrode formed thereon react with each other by a high temperature process, characteristics of the semiconductor device may be reduced or prevented from being degraded.
    Type: Application
    Filed: December 1, 2006
    Publication date: July 19, 2007
    Inventors: Seok-Jun Won, Ju-Youn Kim, Weon-Hong Kim
  • Patent number: 7232492
    Abstract: There is provided a method of forming a thin film for providing improved fabrication productivity. The method includes introducing a semiconductor substrate into a process chamber. A process thin film is formed on the semiconductor substrate, in which a chamber coating layer is formed on inner walls of the process chamber while the process thin film is formed. The semiconductor substrate is removed from the process chamber. A stress relief layer is formed on the chamber coating layer. After all of the above operations are repeatedly performed at least one time, an in-situ cleaning is performed on the chamber coating layer and the stress relief layer, which are alternately formed in stack on the inner walls of the process chamber.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: June 19, 2007
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Seok-Jun Won, Weon-Hong Kim, Dae-Jin Kwon
  • Publication number: 20070111506
    Abstract: Integrated circuit devices including metal-insulator-metal (MIM) capacitors are provided. The MIM capacitors may include an upper electrode having first and second layers. The first layer of the upper electrode includes a physical vapor deposition (PVD) upper electrode and the second layer of the upper electrode includes an ionized PVD (IPVD) upper electrode on the PVD upper electrode. Related methods are also provided.
    Type: Application
    Filed: November 7, 2006
    Publication date: May 17, 2007
    Inventors: Dae-Jin Kwon, Jung-Min Park, Seok-Jun Won, Min-Woo Song, Weon-hong Kim, Ju-youn Kim
  • Publication number: 20070111496
    Abstract: Semiconductor devices having a dual stacked MIM capacitor and methods of fabricating the same are disclosed. The semiconductor device includes a dual stacked MIM capacitor formed on the semiconductor substrate. The dual stacked MIM capacitor includes a lower plate positioned, an upper plate electrically connected to the lower plate and positioned above the lower plate, and an intermediate plate interposed between the lower plate and the upper plate. An upper interconnection line is positioned at the same level as the upper plate. The upper interconnection line is electrically connected to the intermediate plate. As a result, the upper plate may be formed by a damascene process.
    Type: Application
    Filed: January 5, 2007
    Publication date: May 17, 2007
    Inventor: Seok-Jun Won
  • Publication number: 20070102746
    Abstract: A semiconductor integrated circuit device includes a first interlayer insulation film having a contact therein. The contact has an upper surface and including a void therein having an open upper portion. The device further includes a plasma damage reduction unit including a lower electrode conformably on the void of the contact and on the upper surface of the contact, a dielectric film on the lower electrode, and an upper electrode on the dielectric film. The thickness of the portion of the dielectric film in the void is smaller than the thickness of the portion of the dielectric film on the upper surface of the contact.
    Type: Application
    Filed: November 6, 2006
    Publication date: May 10, 2007
    Inventors: Seok-Jun Won, Min-Woo Song, Weon-Hong Kim
  • Patent number: 7203052
    Abstract: A MEMS tunable capacitor and method of fabricating the same, includes a plurality of fixed charge plates on a substrate, the plurality of fixed charge plates having a same height, being arranged in a shape of comb-teeth and being electrically connected to one another, a capacitor dielectric layer covering the plurality of fixed charge plates, a movable charge plate structure spaced apart from the capacitor dielectric layer, and arranged on the plurality of fixed charge plates, wherein the movable charge plate structure includes a plurality of movable charge plates arranged corresponding the plurality of fixed charge plates, and an actuator connected to the movable charge plate structure allowing the movable charge plate structure to move in a horizontal direction.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: April 10, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Jun Won, Kang-soo Chu, Weon-Hong Kim
  • Publication number: 20070077722
    Abstract: Embodiments of the invention provide flat-type capacitors that prevent degradation of the dielectric layer, thereby improving the electrical properties of the capacitor. The capacitor includes a lower interconnection formed in a predetermined portion of a semiconductor substrate, a lower electrode formed on the lower interconnection that is electrically coupled to the lower interconnection; a concave dielectric layer formed on the lower electrode; a concave upper electrode formed on the dielectric layer; a first upper interconnection that is electrically coupled to the lower interconnection; and a second upper interconnection that is coupled to the upper electrode. The concave upper electrode is larger than the lower electrode.
    Type: Application
    Filed: December 8, 2006
    Publication date: April 5, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Seok-Jun WON
  • Patent number: 7199003
    Abstract: In a method of manufacturing a capacitor of a semiconductor device and an apparatus therefor, dielectric layers are deposited using only a source gas without a reactant gas and a curing process is performed a single time. As a result, process simplification, yield improvement, and equipment simplification are achieved. In a stand-alone memory or an embedded memory, the step coverage is enhanced and oxidation of a storage node contact plug is prevented. Also, in an analog capacitor, an RF capacitor, or a high-voltage capacitor, which uses thicker dielectric layers than the stand-alone capacitor or the embedded capacitor, the manufacturing process is greatly simplified.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: April 3, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-kuk Jeong, Myong-geun Yoon, Seok-jun Won, Dae-jin Kwon
  • Patent number: 7180117
    Abstract: Embodiments of the invention provide flat-type capacitors that prevent degradation of the dielectric layer, thereby improving the electrical properties of the capacitor. The capacitor includes a lower interconnection formed in a predetermined portion of a semiconductor substrate, a lower electrode formed on the lower interconnection that is electrically coupled to the lower interconnection; a concave dielectric layer formed on the lower electrode; a concave upper electrode formed on the dielectric layer; a first upper interconnection that is electrically coupled to the lower interconnection; and a second upper interconnection that is coupled to the upper electrode. The concave upper electrode is larger than the lower electrode.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: February 20, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-Jun Won
  • Patent number: 7180120
    Abstract: Semiconductor devices having a dual stacked MIM capacitor and methods of fabricating the same are disclosed. The semiconductor device includes a dual stacked MIM capacitor formed on the semiconductor substrate. The dual stacked MIM capacitor includes a lower plate positioned, an upper plate electrically connected to the lower plate and positioned above the lower plate, and an intermediate plate interposed between the lower plate and the upper plate. An upper interconnection line is positioned at the same level as the upper plate. The upper interconnection line is electrically connected to the intermediate plate. As a result, the upper plate may be formed by a damascene process.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: February 20, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-Jun Won
  • Publication number: 20070034988
    Abstract: A metal-insulator-metal (MIM) capacitor for an integrated circuit may be provided on the interlayer insulating layer and covered by a inter-metal dielectric (IMD) layer. This IMD layer has at least a first opening therein that exposes an upper surface of a first electrode of the MIM capacitor. This first opening is filled with a first copper damascene interconnect pattern, which may in some embodiments be part of a dual-damascene copper interconnect structure associated with a first and lowermost level of metallization (e.g., M1 wiring layer). This first copper damascene interconnect pattern may have an upper surface that is planar with an upper surface of the IMD layer and a bottom surface that is in contact with the upper surface of the first electrode of the MIM capacitor.
    Type: Application
    Filed: July 13, 2006
    Publication date: February 15, 2007
    Inventors: Seok-Jun Won, Ju Kim, Min Song
  • Publication number: 20070026688
    Abstract: Example embodiments of the present invention relate to a method of forming a dielectric thin film and a method of fabricating a semiconductor memory device having the same. Other example embodiments of the present invention relate to a method of forming a ZrO2 thin film and a method of fabricating a capacitor of a semiconductor memory device using the ZrO2 thin film as a dielectric layer. A method of forming a ZrO2 thin film may include supplying a zirconium precursor on a substrate maintained at a desired temperature, thereby forming a chemisorption layer of the precursor on the substrate. The zirconium precursor may be a tris(N-ethyl-N-methylamino)(tert-butoxy) zirconium precursor. The substrate having the chemisorption layer of the precursor may be exposed to the plasma atmosphere of oxygen-containing gas for a desired time, thereby forming a Zr oxide layer on the substrate, and a method of fabricating a capacitor of a semiconductor memory device having the ZrO2 thin film.
    Type: Application
    Filed: July 13, 2006
    Publication date: February 1, 2007
    Inventors: Min-Woo Song, Seok-Jun Won, Weon-Hong Kim, Dae-Jin Kwon, Jung-Min Park