Patents by Inventor Seok-Jun Won

Seok-Jun Won has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050170196
    Abstract: A method of cleaning a reaction chamber using a substrate having a metal catalyst thereon is disclosed. The method includes preparing a substrate having a catalyst layer to activate a cleaning gas. The substrate is introduced into the reaction chamber. Next, a cleaning gas is introduced into the reaction chamber. Contaminations in the reaction chamber are exhausted. The substrate having a metal catalyst layer is also disclosed.
    Type: Application
    Filed: February 1, 2005
    Publication date: August 4, 2005
    Inventors: Seok-Jun Won, Weon-Hong Kim, Min-Woo Song
  • Publication number: 20050152094
    Abstract: In a capacitor, and a method of fabricating the same, the capacitor includes a lower electrode, a dielectric layer on the lower electrode, and an upper electrode on the dielectric layer, wherein the dielectric layer includes a lower dielectric region contacting the lower electrode, an upper dielectric region contacting the upper electrode, and at least one middle dielectric region between the lower dielectric region and the upper dielectric region, the at least one middle dielectric region having a less crystalline region than both the lower dielectric region and the upper dielectric region.
    Type: Application
    Filed: January 11, 2005
    Publication date: July 14, 2005
    Inventors: Yong-kuk Jeong, Jung-Hyoung Lee, Seok-Jun Won, Dae-Jin Kwon, Weon-Hong Kim, Min-woo Song
  • Publication number: 20050130427
    Abstract: There is provided a method of forming a thin film for providing improved fabrication productivity. The method includes introducing a semiconductor substrate into a process chamber. A process thin film is formed on the semiconductor substrate, in which a chamber coating layer is formed on inner walls of the process chamber while the process thin film is formed. The semiconductor substrate is removed from the process chamber. A stress relief layer is formed on the chamber coating layer. After all of the above operations are repeatedly performed at least one time, an in-situ cleaning is performed on the chamber coating layer and the stress relief layer, which are alternately formed in stack on the inner walls of the process chamber.
    Type: Application
    Filed: December 9, 2004
    Publication date: June 16, 2005
    Inventors: Seok-Jun Won, Weon-Hong Kim, Dae-Jin Kwon
  • Publication number: 20050118335
    Abstract: A method of forming a thin ruthenium-containing layer includes performing a CVD process using butyl ruthenoscene as a ruthenium source material. The thin ruthenium-containing layer may be formed by a one-step or two-step CVD process. The one-step CVD process is performed under a constant oxygen flow rate and a constant deposition pressure. The two-step CVD process includes forming a seed layer and forming a main layer, each of which is performed under a different process condition of a deposition temperature, an oxygen flow rate, and a deposition pressure.
    Type: Application
    Filed: December 16, 2004
    Publication date: June 2, 2005
    Inventors: Soon-Yeon Park, Cha-Young Yoo, Seok-Jun Won
  • Publication number: 20050087879
    Abstract: A logic device having a vertically extending MIM capacitor between interconnect layers includes a semiconductor substrate. A lower interconnect layer is located over the semiconductor substrate, and an upper interconnect layer is located over the lower interconnect layer. A U-shaped lower metal plate is interposed between the lower interconnect layer and the upper interconnect layer. The U-shaped lower metal plate directly contacts the lower interconnect layer. The capacitor dielectric layer covers the inner surface of the lower metal plate. Further, the capacitor dielectric layer has an extension portion interposed between the brim of the lower metal plate and the upper interconnect layer. An upper metal plate covers the inner surface of the capacitor dielectric layer. The upper metal plate is in contact with the upper interconnect layer and is confined by the capacitor dielectric layer.
    Type: Application
    Filed: October 20, 2004
    Publication date: April 28, 2005
    Inventors: Seok-Jun Won, Yong-Kuk Jeong, Dae-Jin Kwon, Min-Woo Song, Weon-Hong Kim
  • Patent number: 6876029
    Abstract: Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: April 5, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Hwan Lee, Sang-Hyeop Lee, Young-Sun Kim, Se-Jin Shim, You-Chan Jin, Ju-Tae Moon, Jin-Seok Choi, Young-Min Kim, Kyung-Hoon Kim, Kab-Jin Nam, Young-Wook Park, Seok-Jun Won, Young-Dae Kim
  • Publication number: 20050063141
    Abstract: There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer.
    Type: Application
    Filed: June 23, 2004
    Publication date: March 24, 2005
    Inventors: Yong-Kuk Jeong, Seok-Jun Won, Dae-Jin Kwon, Weon-Hong Kim
  • Patent number: 6844610
    Abstract: Methods are provided for forming an integrated circuit device including a resistor pattern having a desired resistance value. A low resistive layer is formed on an integrated circuit substrate. An insulating layer is formed on the low resistive layer opposite the integrated circuit substrate. A high resistive layer, which may have a specific resistance of at least about a hundred ??•cm, is formed on the insulating layer opposite the low resistive layer. The low resistive layer, the insulating layer and the high resistive layer define the resistor pattern in a region of the integrated circuit substrate. Integrated circuit devices including resistor patterns as provided by the methods are also provided and methods for forming metal contacts to the resistor pattern are also provided.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: January 18, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Jun Won, Young-Wook Park
  • Publication number: 20050001318
    Abstract: An electrical interconnection for a highly integrated semiconductor device includes a first insulation layer having at least a first recessed portion on a substrate. The first recessed portion is filled with metal to form a first metal pattern. A diffusion barrier layer including aluminum oxide of high light transmittance is provided on the first insulation layer and the first metal pattern for preventing metal from diffusing. An insulating interlayer including a second recessed portion for exposing an upper surface of the first metal pattern is provided on the diffusion barrier layer. The second recessed portion is filled with metal to form a second metal pattern. The electrical interconnection may be used with an image sensor. The metal may be copper. High light transmittance of the diffusion barrier layer ensures external light reaches the photodetector. The aluminum oxide of the diffusion barrier layer reduces parasitic capacitance of the electrical interconnections.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 6, 2005
    Inventor: Seok-Jun Won
  • Publication number: 20050003089
    Abstract: A method of forming a carbon nano-material layer may involve a cyclic deposition technique. In the method, a chemisorption layer or a chemical vapor deposition layer may be formed on a substrate. Impurities may be removed from the chemisorption layer or the chemical vapor deposition layer to form a carbon atoms layer on the substrate. More than one carbon atoms layer may be formed by repeating the method.
    Type: Application
    Filed: June 3, 2004
    Publication date: January 6, 2005
    Inventors: Seok-Jun Won, Dae-Jin Kwon, Yong-Kuk Jeong
  • Publication number: 20040175905
    Abstract: Provided is an atomic layer deposition (ALD) method for forming a thin film using two types of reactants that are different in surface adsorptivity for a source material. According to the ALD method, first, a source material is fed into a reaction chamber and then undergoes first purging. Next, a first reactant with good surface adsorptivity for the source material and a second reactant with poor surface adsorptivity for the source material are fed into the reaction chamber. The second reactant may be fed simultaneously with the first reactant or after the purging of the first reactant. Next, a radio frequency is applied to the reaction chamber to thereby transform the second reactant into a plasma state. Next, the reaction chamber is subjected to a second purging. If the thickness of a deposited film is not sufficient, the above-described processes are repeated.
    Type: Application
    Filed: March 3, 2004
    Publication date: September 9, 2004
    Inventors: Seok-Jun Won, Yong-Kuk Jeong, Dae-Jin Kwon
  • Publication number: 20040175492
    Abstract: A ruthenium (Ru) film is formed on a substrate as part of a two-stage methodology. During the first stage, the Ru film is formed on the substrate in a manner in which the Ru nucleation rate is greater than the Ru growth rate. During the second stage, the Ru film is formed on the substrate in a manner in which the Ru growth rate is greater than the Ru nucleation rate.
    Type: Application
    Filed: March 15, 2004
    Publication date: September 9, 2004
    Inventors: Seok-jun Won, Cha-young Yoo
  • Publication number: 20040171212
    Abstract: In a method of manufacturing a capacitor by performing a multi-stepped wet treatment on the surface of a metal electrode, a lower metal electrode of a capacitor is formed, and a primary wet treatment is performed on the surface of the lower metal electrode to remove unwanted surface oxides that may exist on the surface of the lower metal electrode. A secondary wet treatment is then performed on the surface of the lower metal electrode by using a different etchant than the etchant used in the primary wet treatment, in order to remove unwanted surface organic materials that may exist on the surface of the lower metal electrode. A dielectric layer is then formed on the lower metal electrode using a high-k dielectric material. An upper metal electrode is formed on the dielectric layer.
    Type: Application
    Filed: February 11, 2004
    Publication date: September 2, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seok-jun Won, Jung-hee Chung, Yong-kuk Jeong, Se-hoon Oh, Dae-jin Kwon, Cha-young Yoo
  • Publication number: 20040149991
    Abstract: Embodiments of the invention provide flat-type capacitors that prevent degradation of the dielectric layer, thereby improving the electrical properties of the capacitor. The capacitor includes a lower interconnection formed in a predetermined portion of a semiconductor substrate, a lower electrode formed on the lower interconnection that is electrically coupled to the lower interconnection; a concave dielectric layer formed on the lower electrode; a concave upper electrode formed on the dielectric layer; a first upper interconnection that is electrically coupled to the lower interconnection; and a second upper interconnection that is coupled to the upper electrode. The concave upper electrode is larger than the lower electrode.
    Type: Application
    Filed: September 30, 2003
    Publication date: August 5, 2004
    Inventor: Seok-Jun Won
  • Publication number: 20040141390
    Abstract: Provided is a capacitor of a semiconductor device. The capacitor includes a capacitor lower electrode disposed on a semiconductor substrate. A first dielectric layer comprising aluminum oxide (Al2O3) is disposed on the capacitor lower electrode. A second dielectric layer comprising a material having a higher dielectric constant than that of aluminum oxide is disposed on the first dielectric layer. A third dielectric layer comprising aluminum oxide is disposed on the second dielectric layer. A capacitor upper electrode is disposed on the third dielectric layer. The capacitor of the present invention can improve electrical properties. Thus, power consumption can be reduced and capacitance per unit area is high enough to achieve high integration.
    Type: Application
    Filed: December 29, 2003
    Publication date: July 22, 2004
    Inventors: Seok-Jun Won, Myong-geun Yoon, Yong-Kuk Jeong, Dae-jin Kwon
  • Patent number: 6750092
    Abstract: A ruthenium (Ru) film is formed on a substrate as part of a two-stage methodology. During the first stage, the Ru film is formed on the substrate in a manner in which the Ru nucleation rate is greater than the Ru growth rate. During the second stage, the Ru film is formed on the substrate in a manner in which the Ru growth rate is greater than the Ru nucleation rate.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: June 15, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-jun Won, Cha-young Yoo
  • Publication number: 20040106252
    Abstract: In a method of manufacturing a capacitor of a semiconductor device and an apparatus therefor, dielectric layers are deposited using only a source gas without a reactant gas and a curing process is performed a single time. As a result, process simplification, yield improvement, and equipment simplification are achieved. In a stand-alone memory or an embedded memory, the step coverage is enhanced and oxidation of a storage node contact plug is prevented. Also, in an analog capacitor, an RF capacitor, or a high-voltage capacitor, which uses thicker dielectric layers than the stand-alone capacitor or the embedded capacitor, the manufacturing process is greatly simplified.
    Type: Application
    Filed: October 29, 2003
    Publication date: June 3, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yong-Kuk Jeong, Myong-Geun Yoon, Seok-Jun Won, Dae-Jin Kwon
  • Publication number: 20040084709
    Abstract: A capacitor includes an upper electrode formed by physical vapor deposition and chemical vapor deposition. The upper electrode of the capacitor may include a first upper electrode formed by chemical vapor deposition and a second upper electrode formed by physical vapor deposition. Alternatively, the upper electrode may include a first upper electrode formed by physical vapor deposition and a second upper electrode formed by chemical vapor deposition. The upper electrode of the capacitor is formed through two steps using chemical vapor deposition and physical vapor deposition. Therefore, the upper electrode can be thick and rapidly formed, whereby electrical characteristics of the upper electrode are not deteriorated.
    Type: Application
    Filed: July 29, 2003
    Publication date: May 6, 2004
    Applicant: Samsung Electronics Co, Ltd.
    Inventors: Hong-Ki Kim, Ho-Kyu Kang, Moon-Han Park, Myong-Geun Yoon, Seok-Jun Won, Yong-Kuk Jeong, Kyung-Hun Kim
  • Publication number: 20040070019
    Abstract: The effective area of a MIM capacitor is increased by forming a lower electrode that includes hemispherical grain lumps. The hemispherical grain lumps are formed by heat-treating a metal layer in an oxygen and/or nitrogen atmosphere, thus oxidizing the surface of the metal layer or growing the crystal grains of the metal layer. The MIM capacitor may be formed of Pt, Ru, Rh, Os, Ir, or Pd, and the hemispherical grain lumps may be formed of Pt, Ru, Rh, Os, Ir, or Pd. Since the metal layer is primarily heat-treated during the formation of the lower electrode, it is possible to reduce the degree to which the surface morphology of the lower electrode is rapidly changed due to a heat treatment subsequent to forming a dielectric layer and an upper electrode.
    Type: Application
    Filed: November 17, 2003
    Publication date: April 15, 2004
    Inventors: Jae-Hyun Joo, Wan-Don Kim, Seok-Jun Won, Soon-Yeon Park
  • Publication number: 20040065938
    Abstract: Integrated circuit capacitors are provided having an electrically insulating electrode support layer having an opening therein on an integrated circuit substrate. A U-shaped lower electrode is provided in the opening and a first capacitor dielectric layer extends on an inner surface and an outer portion of the U-shaped lower electrode. A second capacitor dielectric layer extends between the outer portion of the U-shaped lower electrode and the first capacitor dielectric and also extends between the outer portion of the U-shaped lower electrode and an inner sidewall of the opening. An upper electrode extends on the first dielectric layer.
    Type: Application
    Filed: September 17, 2003
    Publication date: April 8, 2004
    Inventors: Seok-Jun Won, Cha-Young Yoo