Abstract: An apparatus and method with in-memory computing (IMC) are provided. An in-memory computing (IMC) circuit includes a plurality of memory banks, each memory bank including a bit cell configured to store a weight value and an operator configured to receive an input value, the operator being connected to the bit cell such that the operator upon receiving the input value outputs a logic operation result between the input value and the weight value, and a logic gate configured to receive the logic operation result of each of the memory banks.

Abstract: A method and memory device with in-memory computing defection detection is disclosed. A memory device includes a memory including banks, wherein each bank includes a respective plurality of bit-cells, an in-memory computation (IMC) operator configured to perform an IMC operation between first data while the first data is in the bit-cells of the memory and second data received as input to the memory device, wherein the banks share the operator, and wherein the memory device is configured to: generate a first test pattern that is stored in the memory and generate a second test pattern applied to the IMC operator, and based thereon determine whether a defect has occurred in either the memory or the operator, and perform a repair based on the determination that a defect has occurred.

Abstract: A three-dimensional semiconductor device includes gate electrodes including pad regions sequentially lowered by a first step portion in a first direction and sequentially lowered by a second step portion in a second direction perpendicular to the first direction, the second step portion being lower than the first step portion, wherein a length of a single pad region among pad regions sequentially lowered by the second step portion in the second direction is less than a length of a remainder of the pad regions in the second direction.

Abstract: Vertical memory devices and methods of forming the same are provided. The devices may include a gate line structure including gate lines that are stacked in a first direction and extend in a second direction. The device may also include a first step pattern structure including extended gate lines extending from the gate lines and including first step layers and a second step pattern structure contacting the first step pattern structure, including the extended gate lines and including second step layers. An n-th extended gate line (n is an even number) may be disposed at an upper portion of each of the first step layers, and an (n-1)-th extended gate line may be disposed at an upper portion of each of the second step layers. Each of exposed portions of the (n-1)-th extended gate lines serves as a pad region, and the pad regions have different areas.

Abstract: Vertical memory devices and methods of forming the same are provided. The devices may include a gate line structure including gate lines that are stacked in a first direction and extend in a second direction. The device may also include a first step pattern structure including extended gate lines extending from the gate lines and including first step layers and a second step pattern structure contacting the first step pattern structure, including the extended gate lines and including second step layers. An n-th extended gate line (n is an even number) may be disposed at an upper portion of each of the first step layers, and an (n-1)-th extended gate line may be disposed at an upper portion of each of the second step layers. Each of exposed portions of the (n-1)-th extended gate lines serves as a pad region, and the pad regions have different areas.

Abstract: A three-dimensional semiconductor device includes gate electrodes including pad regions sequentially lowered by a first step portion in a first direction and sequentially lowered by a second step portion in a second direction perpendicular to the first direction, the second step portion being lower than the first step portion, wherein a length of a single pad region among pad regions sequentially lowered by the second step portion in the second direction is less than a length of a remainder of the pad regions in the second direction.

Abstract: A three-dimensional semiconductor device includes gate electrodes including pad regions sequentially lowered by a first step portion in a first direction and sequentially lowered by a second step portion in a second direction perpendicular to the first direction, the second step portion being lower than the first step portion, wherein a length of a single pad region among pad regions sequentially lowered by the second step portion in the second direction is less than a length of a remainder of the pad regions in the second direction.

Abstract: A vertical memory device may include a plurality of word lines spaced apart in a first direction, each extending in a second direction perpendicular to the first direction and having a first width in a third direction perpendicular to the first and second directions, a dummy word line over an uppermost word line, including an opening and having a portion thereof with the first width in the third direction, a first string selection line (SSL) and a second string selection line (SSL) over the dummy word line, the first and second SSLs being at substantially the same level along the first direction, each of the first and second SSLs having a second width less than the first width in the third direction, and a plurality of vertical channel structures, each through the word lines, the dummy word line, and one of the first and second SSLs.

Abstract: A three-dimensional semiconductor device includes gate electrodes including pad regions sequentially lowered by a first step portion in a first direction and sequentially lowered by a second step portion in a second direction perpendicular to the first direction, the second step portion being lower than the first step portion, wherein a length of a single pad region among pad regions sequentially lowered by the second step portion in the second direction is less than a length of a remainder of the pad regions in the second direction.

Abstract: A vertical memory device may include a plurality of word lines spaced apart in a first direction, each extending in a second direction perpendicular to the first direction and having a first width in a third direction perpendicular to the first and second directions, a dummy word line over an uppermost word line, including an opening and having a portion thereof with the first width in the third direction, a first string selection line (SSL) and a second string selection line (SSL) over the dummy word line, the first and second SSLs being at substantially the same level along the first direction, each of the first and second SSLs having a second width less than the first width in the third direction, and a plurality of vertical channel structures, each through the word lines, the dummy word line, and one of the first and second SSLs.

Abstract: A vertical memory device may include a plurality of word lines spaced apart in a first direction, each extending in a second direction perpendicular to the first direction and having a first width in a third direction perpendicular to the first and second directions, a dummy word line over an uppermost word line, including an opening and having a portion thereof with the first width in the third direction, a first string selection line (SSL) and a second string selection line (SSL) over the dummy word line, the first and second SSLs being at substantially the same level along the first direction, each of the first and second SSLs having a second width less than the first width in the third direction, and a plurality of vertical channel structures, each through the word lines, the dummy word line, and one of the first and second SSLs.

Abstract: A vertical memory device may include a plurality of word lines spaced apart in a first direction, each extending in a second direction perpendicular to the first direction and having a first width in a third direction perpendicular to the first and second directions, a dummy word line over an uppermost word line, including an opening and having a portion thereof with the first width in the third direction, a first string selection line (SSL) and a second string selection line (SSL) over the dummy word line, the first and second SSLs being at substantially the same level along the first direction, each of the first and second SSLs having a second width less than the first width in the third direction, and a plurality of vertical channel structures, each through the word lines, the dummy word line, and one of the first and second SSLs.

Abstract: Vertical memory devices and methods of forming the same are provided. The devices may include a gate line structure including gate lines that are stacked in a first direction and extend in a second direction. The device may also include a first step pattern structure including extended gate lines extending from the gate lines and including first step layers and a second step pattern structure contacting the first step pattern structure, including the extended gate lines and including second step layers. An n-th extended gate line (n is an even number) may be disposed at an upper portion of each of the first step layers, and an (n?1)-th extended gate line may be disposed at an upper portion of each of the second step layers. Each of exposed portions of the (n?1)-th extended gate lines serves as a pad region, and the pad regions have different areas.