Abstract: A dual polarization antenna is disclosed in at least one embodiment of the present disclosure, including a base substrate, a power feeding unit supported on the base substrate, and a radiating plate supported on the power feeding unit, wherein the first feeding substrate includes a first insulating substrate supported on the base substrate, and a first feed line attached to the first insulating substrate and configured to supply a first reference phase signal to a first point on the radiating plate and to supply to a second point on the radiating plate, a first reverse phase signal having a reverse phase relative to the first reference phase signal, and wherein the second feeding substrate includes a second insulating substrate supported on the base substrate, and a second feed line attached to the first insulating substrate and configured to supply a second reference phase signal to a third point on the radiating plate and to supply to a fourth point on the radiating plate, a second reverse phase signal havi

Abstract: A peridynamic method having an added mirroring node according to embodiments of the present invention includes: a first step of calculating a shape tensor of a first node; a second step of calculating force state vectors of the first node and each of a plurality of second nodes by using the shape tensor; and a third step of calculating a peridynamic motion equation of the first node by using the force state vectors. The first node is a node located on a boundary of a structure and has a predetermined size horizon region, the plurality of second nodes is nodes in the horizon region, the plurality of second nodes includes one or more third nodes, and the third node is a second node having no node at a point which is origin-symmetrical based on the first node among the plurality of second nodes. In the first step, the shape tensor is calculated by using a position value in which the third node is origin-symmetrical based on the first node.

Abstract: A system-on-chip (SoC) may comprise a semiconductor substrate; a first circuitry, disposed on the semiconductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network (ANN) model; a second circuitry, disposed on the semiconductor substrate, provided for a second NPU configured to perform operations of an ANN model; and a third circuitry, disposed on the semiconductor substrate, configured to generate a control signal to selectively output one or more clock signals, wherein each of the first NPU and the second NPU may include a plurality of processing elements (PEs), and the plurality of PEs may include an adder, a multiplier, and an accumulator, and wherein the one or more clock signals may include an original clock signal and one or more phase-delayed clock signals based on a phase of the original clock signal.

Abstract: A neural processing unit may comprise a first circuitry including a plurality of processing elements (PEs) configured to perform operations of an artificial neural network model, the plurality of PEs including an adder, a multiplier, and an accumulator, and a clock signal supply circuitry configured to output one or more clock signals. When the plurality of PEs include a first group of PEs and a second group of PEs, a first clock signal among the one or more clock signals, may be supplied to the first group of PEs and a second clock signal among the one or more clock signals, may be supplied to the second group of PEs. At least one of the first and second clock signals may have a preset phase based on a phase of an original clock signal.

Abstract: A neural processing unit may comprise a first circuit configured to perform operations for an artificial neural network (ANN) model, and arranged for a plurality of groups of processing elements (PEs) including a plurality of PEs; a second circuit arranged to output a plurality of clock signals to the first circuit; a third circuit configured to measure a ratio of peak power and average power of at least the first circuit; and a fourth circuit, arranged to dynamically calibrate a phase of at least one of the plurality of clock signals of the second circuit based on the ratio of peak power and average power measured in the third circuit.

Abstract: A method for manufacturing a gas diffusion layer for a fuel cell wherein carbon nanotubes are impregnated into Korean paper, thereby enhancing electroconductivity, and a gas diffusion layer manufactured thereby. The method for manufacturing a gas diffusion layer for a fuel cell which is to manufacture a gas diffusion layer as a constituent member of a unit cell in a fuel cell, includes a support preparation step of preparing a support with Korean paper; a dispersion preparation step of dispersing a carbon substance in a solvent to form a dispersion, a coating step of coating the support with the dispersion, and a thermal treatment step of thermally treating the dispersion-coated support to fix the carbon substance to the support.

Abstract: The present invention relates to a culture device and culture method for culturing a 3D cell aggregation and, specifically, to an overall technique for effectively culturing a 3D cell aggregation by using a culture device including a porous microwell, a membrane, and other additive components.

Abstract: The present invention relates to a peptide with anti-inflammatory activity, wherein the peptide comprises SEQ ID NO: 1, the peptide has above 80% homology of amino acid sequence with above-mentioned sequence, or the peptide is the fragment of the above-mentioned peptides. The present invention also relates to an inflammatory composition comprising the above mentioned peptides. According to the present invention, a peptide comprising a sequence of SEQ ID NO: 1 has an outstanding efficacy in both suppressing inflammation and in prophylactic means. Therefore, the composition comprising the peptide of this invention can be used as anti-inflammatory pharmaceutical composition or as cosmetic composition, in turn, treating and preventing a variety of different types of inflammatory diseases.

Abstract: An apparatus for embedding a sentence feature vector according to an embodiment includes a sentence acquisitor configured to acquire a first sentence and a second sentence, each including one or more words; a vector extractor configured to extract a first feature vector corresponding to the first sentence and a second feature vector corresponding to the second sentence by independently inputting each of the first sentence and the second sentence into a feature extraction network; and a vector compressor configured to compress the first feature vector and the second feature vector into a first compressed vector and a second compressed vector, respectively, by independently inputting each of the first feature vector and the second feature vector into a convolutional neural network (CNN)-based vector compression network.

Abstract: A memory controller comprising a DMA master device configured to provide a first data group to a non-volatile memory (NVM) device, a program buffer memory configured to temporarily store the first data group before the DMA master device provides the first data group to the NVM device, an exclusive OR computing circuit configured to perform an exclusive OR computation and an accumulation on a plurality of data included in the first data group provided from the program buffer memory to generate a first recovery data, after the DMA master device provides the first data group to the NVM device, and a buffer slave device including a first program recovery buffer memory configured to store the first recovery data and provide the first recovery data from the first program recovery buffer memory to the program buffer memory, in response to a program failure signal, may be provided.

Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.

Abstract: A system may comprise a neural processing unit (NPU) including a plurality of processing elements (PEs) capable of performing computations for at least one artificial neural network (ANN) model; and a switching circuit. The switching circuit may be configured to select one clock signal among a plurality of clock signals having different frequencies, and supply the selected clock signal to the NPU. The one clock signal may be selected based on a utilization rate of the plurality of PEs for a particular layer among a plurality of layers of the at least one ANN model.

Abstract: A system may comprise a neural processing unit (NPU) including at least one memory and a plurality of processing elements (PEs) capable of performing operations for at least one artificial neural network (ANN) model. The plurality of PEs may include an adder, a multiplier, and an accumulator. The plurality of PEs may include a first group of PEs configured to operate on a first portion of a clock signal and a second group of PEs configured to operate on a second portion of the clock signal.

Abstract: A lighting device includes a substrate having a plurality of flat portions and a non-flat portion disposed between the flat portions, a plurality of light emitting sources disposed on the substrate, a fluorescent substrate layer covering one or more light emitting sources and converting a wavelength of a light from the light emitting source, and a connection line disposed on the substrate and electrically connecting the light emitting sources adjacent to each other between the adjacent light emitting sources. The substrate has a first end and a second end are arranged at different distance from a central axis.

Abstract: A system-on-chip (SoC) may comprise a semiconductor substrate; a first circuitry, disposed on the semiconductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network (ANN) model; a second circuitry, disposed on the semiconductor substrate, provided for a second NPU configured to perform operations of an ANN model; and a third circuitry, disposed on the semiconductor substrate, configured to generate a control signal to selectively output one or more clock signals, wherein each of the first NPU and the second NPU may include a plurality of processing elements (PEs), and the plurality of PEs may include an adder, a multiplier, and an accumulator, and wherein the one or more clock signals may include an original clock signal and one or more phase-delayed clock signals based on a phase of the original clock signal.

Abstract: Provided are methods and apparatuses for controlling traffic signals of traffic lights in a sub-area by using a neural network model. The method according to an embodiment of the present disclosure may configure state information of a sub-area by using downstream information obtained in a current cycle time for each of a plurality of intersections included in the sub-area. In addition, the method may input the state information to a trained reinforcement learning model, and obtain action information of the sub-area including green times and offsets, by using an output from the trained reinforcement learning model. Furthermore, the method may generate coordinated signal values for applying the action to traffic lights in the sub-area in a subsequent cycle time.

Abstract: A system-on-chip (SoC) may comprise a semi-conductor substrate; a first circuitry, disposed on the semi-conductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network model (ANN); a second circuitry, disposed on the semi-conductor substrate, provided for a second NPU configured to perform operations of an ANN model, each of the first NPU and the second NPU including a plurality of processing elements (PEs), the plurality of PEs including an adder, a multiplier, and an accumulator; and a clock signal supply circuit, disposed on the semi-conductor substrate, configured to output one or more clock signals, wherein a first clock signal among the one or more clock signals may be supplied to the first NPU, and a second clock signal among the one or more clock signals may be supplied to the second NPU.

Abstract: A neural processing unit may comprise a first circuitry including a plurality of processing elements (PEs) configured to perform operations of an artificial neural network model, the plurality of PEs including an adder, a multiplier, and an accumulator, and a clock signal supply circuitry configured to output one or more clock signals. When the plurality of PEs include a first group of PEs and a second group of PEs, a first clock signal among the one or more clock signals, may be supplied to the first group of PEs and a second clock signal among the one or more clock signals, may be supplied to the second group of PEs. At least one of the first and second clock signals may have a preset phase based on a phase of an original clock signal.

Abstract: A system may comprise a neural processing unit (NPU) including at least one memory and a plurality of processing elements (PEs) capable of performing operations for at least one artificial neural network (ANN) model. The plurality of PEs may include an adder, a multiplier, and an accumulator. The plurality of PEs may include a first group of PEs configured to operate on a first portion of a clock signal and a second group of PEs configured to operate on a second portion of the clock signal.

Abstract: Some aspects of the present disclosure are directed to computerized methods for extracting attributes from product titles. The method may include: retrieving first product identifier comprising at least one tag; determining, based on the at least one tag, a number of quantity related tags; flagging the product identifier as having a quantity based on an analysis of the quantity related tags; comparing the at least one tag and quantity of the first product identifier with at least one tag and quantity associated with a second product identifier; generating, based on the comparison, at least one similarity value between the first product identifier and the second product identifier; and transmitting instructions to at least one user device, wherein the instructions cause the at least one user device to display the at least one similarity value.